Agilex™ 7 Hard Processor System Component Reference Manual

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ID 683581
Date 10/08/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Agilex™ 7 Hard Processor System Component 2. Configuring the Agilex™ 7 Hard Processor System Component 3. Simulating the Agilex™ 7 HPS Component 4. Simulating the Agilex™ 7 HPS bridges (H2F, LWH2F, F2H)
1. Introduction to the Agilex™ 7 Hard Processor System Component x
1.1. Cortex*-A53 MPCore Processor 1.2. CoreSight* Debug Components 1.3. Interconnect 1.4. FPGA Bridges 1.5. Memory Controllers 1.6. Support Peripherals 1.7. Introduction to the HPS Component Revision History
1.6. Support Peripherals x
1.6.1. Interface Peripherals 1.6.2. On-Chip Memories
2. Configuring the Agilex™ 7 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. FPGA Interfaces 2.3. HPS Clocks and Resets 2.4. HPS EMIF 2.5. I/O Delays 2.6. Pin MUX and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the HPS Component Revision History
2.2. FPGA Interfaces x
2.2.1. General Interfaces 2.2.2. HPS-FPGA AXI Bridges 2.2.3. HPS Boot Source 2.2.4. DMA Controller Interface 2.2.5. Interrupts
2.2.1. General Interfaces x
2.2.1.1. Enable MPU Standby and Event Interfaces 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable FPGA Cross Trigger Interface 2.2.1.6. Enable DDR Arm* Trace Bus (ATB)
2.2.2. HPS-FPGA AXI Bridges x
2.2.2.1. FPGA-to-HPS Slave Interface 2.2.2.2. HPS to FPGA AXI-4 Master Interface 2.2.2.3. Lightweight HPS to FPGA Master Interface
2.2.5. Interrupts x
2.2.5.1. FPGA-to-HPS 2.2.5.2. HPS-to-FPGA
2.3. HPS Clocks and Resets x
2.3.1. Input Clocks 2.3.2. Internal Clocks and Output Clocks 2.3.3. Resets
2.3.1. Input Clocks x
2.3.1.1. External Clock Source 2.3.1.2. FPGA-to-HPS Clocks Source 2.3.1.3. Peripheral FPGA Clocks
2.3.2. Internal Clocks and Output Clocks x
2.3.2.1. Main PLL Output Clocks – Desired Frequencies 2.3.2.2. HPS to FPGA User Clocks 2.3.2.3. HPS Peripheral Clocks – Desired Frequencies 2.3.2.4. Clock Sources 2.3.2.5. PLL Report
2.4. HPS EMIF x
2.4.1. Debugging HPS EMIF with the EMIF Debug Toolkit
2.6. Pin MUX and Peripherals x
2.6.1. Pin Mux GUI 2.6.2. Pin Mux Report 2.6.3. EMAC ptp Interface
2.6.1. Pin Mux GUI x
2.6.1.1. Auto-Place IP 2.6.1.2. Advanced
3. Simulating the Agilex™ 7 HPS Component x
3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the Agilex™ 7 HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer 3.1.3. RTL Simulation Setup Scripts
3.1.3. RTL Simulation Setup Scripts x
3.1.3.1. QuestaSIM* Simulation Steps 3.1.3.2. Cadence® Xcelium* Simulation Steps 3.1.3.3. Synopsys* VCS* MX Simulation Steps 3.1.3.4. Riviera-PRO* Simulation Steps 3.1.3.5. VSIM Command Line Aliases and Variables
3.2. Clock and Reset Interfaces x
3.2.1. Clock Interface 3.2.2. Reset Interface
4. Simulating the Agilex™ 7 HPS bridges (H2F, LWH2F, F2H) x
4.1. Setting up the HPS Component for Simulation 4.2. Generating the Testbench System 4.3. Editing the Testbench Scripts 4.4. Running the Testbench 4.5. Simulating the Agilex™ 7 HPS Bridges (H2F, LWH2F, F2H) Revision History
4.3. Editing the Testbench Scripts x
4.3.1. my_simple_tb.sv 4.3.2. test_lwh2f.sv 4.3.3. test_h2f.sv
4.4. Running the Testbench x
4.4.1. Questa*-Altera® FPGA Edition Simulation Steps
1. Introduction to the Agilex™ 7 Hard Processor System Component
2. Configuring the Agilex™ 7 Hard Processor System Component
3. Simulating the Agilex™ 7 HPS Component
4. Simulating the Agilex™ 7 HPS bridges (H2F, LWH2F, F2H)

3.1.2. Generating the HPS Simulation Model in Platform Designer

Note: This section describes how to generate the simulation model when a single .qsys system is in the Quartus® Prime project. It does not describe the method to generate the simulation model when multiple .qsys systems are in the Quartus® Prime project. There are plans to describe this in a future version of this document.

The following steps outline how to generate the simulation model:

  1. In Quartus® Prime Pro Edition software, launch the Platform Designer and open your system design that has been created in the previous section.
  2. In Platform Designer, click on the Generate HDL button.
    Figure 36.  Platform Designer—Generate HDL Button
  3. A Generation Window opens. In the Simulation section, use the Create simulation model dropdown to choose Verilog or VHDL.
  4. Select which of the supported simulators to generate files. (Leaving all the boxes unselected generates files for all simulators.)
    Note: When selecting the Clear output directories for selected generation targets, it erases all files in the output directories including any previous setup scripts.
  5. Click the Generate button.
    Figure 37.  Platform Designer—Select Simulators to Generate
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