Agilex™ 7 Hard Processor System Component Reference Manual

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ID 683581
Date 10/08/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Agilex™ 7 Hard Processor System Component 2. Configuring the Agilex™ 7 Hard Processor System Component 3. Simulating the Agilex™ 7 HPS Component 4. Simulating the Agilex™ 7 HPS bridges (H2F, LWH2F, F2H)
1. Introduction to the Agilex™ 7 Hard Processor System Component x
1.1. Cortex*-A53 MPCore Processor 1.2. CoreSight* Debug Components 1.3. Interconnect 1.4. FPGA Bridges 1.5. Memory Controllers 1.6. Support Peripherals 1.7. Introduction to the HPS Component Revision History
1.6. Support Peripherals x
1.6.1. Interface Peripherals 1.6.2. On-Chip Memories
2. Configuring the Agilex™ 7 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. FPGA Interfaces 2.3. HPS Clocks and Resets 2.4. HPS EMIF 2.5. I/O Delays 2.6. Pin MUX and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the HPS Component Revision History
2.2. FPGA Interfaces x
2.2.1. General Interfaces 2.2.2. HPS-FPGA AXI Bridges 2.2.3. HPS Boot Source 2.2.4. DMA Controller Interface 2.2.5. Interrupts
2.2.1. General Interfaces x
2.2.1.1. Enable MPU Standby and Event Interfaces 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable FPGA Cross Trigger Interface 2.2.1.6. Enable DDR Arm* Trace Bus (ATB)
2.2.2. HPS-FPGA AXI Bridges x
2.2.2.1. FPGA-to-HPS Slave Interface 2.2.2.2. HPS to FPGA AXI-4 Master Interface 2.2.2.3. Lightweight HPS to FPGA Master Interface
2.2.5. Interrupts x
2.2.5.1. FPGA-to-HPS 2.2.5.2. HPS-to-FPGA
2.3. HPS Clocks and Resets x
2.3.1. Input Clocks 2.3.2. Internal Clocks and Output Clocks 2.3.3. Resets
2.3.1. Input Clocks x
2.3.1.1. External Clock Source 2.3.1.2. FPGA-to-HPS Clocks Source 2.3.1.3. Peripheral FPGA Clocks
2.3.2. Internal Clocks and Output Clocks x
2.3.2.1. Main PLL Output Clocks – Desired Frequencies 2.3.2.2. HPS to FPGA User Clocks 2.3.2.3. HPS Peripheral Clocks – Desired Frequencies 2.3.2.4. Clock Sources 2.3.2.5. PLL Report
2.4. HPS EMIF x
2.4.1. Debugging HPS EMIF with the EMIF Debug Toolkit
2.6. Pin MUX and Peripherals x
2.6.1. Pin Mux GUI 2.6.2. Pin Mux Report 2.6.3. EMAC ptp Interface
2.6.1. Pin Mux GUI x
2.6.1.1. Auto-Place IP 2.6.1.2. Advanced
3. Simulating the Agilex™ 7 HPS Component x
3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the Agilex™ 7 HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer 3.1.3. RTL Simulation Setup Scripts
3.1.3. RTL Simulation Setup Scripts x
3.1.3.1. QuestaSIM* Simulation Steps 3.1.3.2. Cadence® Xcelium* Simulation Steps 3.1.3.3. Synopsys* VCS* MX Simulation Steps 3.1.3.4. Riviera-PRO* Simulation Steps 3.1.3.5. VSIM Command Line Aliases and Variables
3.2. Clock and Reset Interfaces x
3.2.1. Clock Interface 3.2.2. Reset Interface
4. Simulating the Agilex™ 7 HPS bridges (H2F, LWH2F, F2H) x
4.1. Setting up the HPS Component for Simulation 4.2. Generating the Testbench System 4.3. Editing the Testbench Scripts 4.4. Running the Testbench 4.5. Simulating the Agilex™ 7 HPS Bridges (H2F, LWH2F, F2H) Revision History
4.3. Editing the Testbench Scripts x
4.3.1. my_simple_tb.sv 4.3.2. test_lwh2f.sv 4.3.3. test_h2f.sv
4.4. Running the Testbench x
4.4.1. Questa*-Altera® FPGA Edition Simulation Steps
1. Introduction to the Agilex™ 7 Hard Processor System Component
2. Configuring the Agilex™ 7 Hard Processor System Component
3. Simulating the Agilex™ 7 HPS Component
4. Simulating the Agilex™ 7 HPS bridges (H2F, LWH2F, F2H)

4.3.2. test_lwh2f.sv

  1. Change directory to <project directory>/simple_tb/simple_tb/sim/ .
  2. Create a file named test_lwh2f.sv and edit with contents as shown below. 
    // test_lwh2f.sv

`timescale 1 ps / 1 ps
import altera_axi_bfm_pkg::*; 

module test_lwh2f#();

`define   lwh2f_test_m  simple_inst.intel_agilex_hps_0.intel_agilex_hps_0. \
			   fpga_interfaces.hps_inst.s2f_module.lwh2f_bfm_gen. \
			   lwh2f_axi4_manager_inst.AXI4MAN.bfm 

localparam A_WIDTH 	= 21;		// interface addr width
localparam D_WIDTH 	= 32;		// interface data width

int i,j;
bit status, f_rw[8], f_incr[8][8];
reg [A_WIDTH-1:0] Addr;
int Data[8];

//---------------------------------------------------------------------------------
//----------------------------  BFM Manager (lwh2f)
//---------------------------------------------------------------------------------
initial begin 

  AlteraAxiTransaction wr_resp_tr, rd_resp_tr;

  Data[0] = 'haaaaaaaa;
  Data[1] = 'hbbbbbbbb;
  Data[2] = 'hcccccccc;
  Data[3] = 'hdddddddd;
  
  $display("\n\n\n *********** START OF  LWH2F testing *********** \n\n\n");
  
  `lwh2f_test_m.m_reset();

///////////////////////////////////// SINGLE WRITES ///////////////////////////////
for (i = 0; i < 4; i++) begin
  $display("\n@%0t**** START OF WRITE #%d TEST ****  LWH2F  *******\n",$time, i);
  Addr = (i * 1<<AXI4_BYTES_4);
  wr_resp_tr = `lwh2f_test_m.manager_bfm_wr_tx( i, Addr );	// id, addr
  wr_resp_tr.set_data_words(Data[i], 0);			// data, index
  wr_resp_tr.set_write_strobes(4'hf, 0);			// strobe, index
  `lwh2f_test_m.put_transaction(wr_resp_tr); 
  `lwh2f_test_m.drive_transaction(); 
  $display("\n@%0t**** END OF   WRITE #%d TEST ****  LWH2F  ********\n",$time, i);
end
///////////////////////////////////// SINGLE READS  ///////////////////////////////
for (i = 0; i < 4; i++) begin
  $display("\n@%0t**** START OF READ  #%d TEST ***   LWH2F  ********\n",$time, i);
  Addr = (i * 1<<AXI4_BYTES_4);
  rd_resp_tr = `lwh2f_test_m.manager_bfm_rd_tx( i, Addr );	// id, addr
  rd_resp_tr.set_size(AXI4_BYTES_4);
  `lwh2f_test_m.put_transaction(rd_resp_tr); 
  `lwh2f_test_m.drive_transaction();
  if (rd_resp_tr.get_data_words(0) == Data[i]) begin
     f_rw[i]=1'b1;
     $display ("value of f_rw[%d] is %b", i, f_rw[i]);
     $display ( "@ %t Read correct data (%h) at address (0x%h)", 
     			$time, Data[i], Addr);
     end 
  else
     $display ( "@ %t Error: Expected data (%h) at address (0x%h), but got %d",
     			$time, Data[i], Addr, rd_resp_tr.get_data_words(0));
  $display("\n@%0t**** END OF   READ  #%d TEST ***   LWH2F   *******\n",$time, i);
end
///////////////////////////////////// INCR WRITES/READS  //////////////////////////
for (i = 0; i < 4; i++) begin
  $display("\n@%0t***** START OF INCR BURST #%d TEST ***   LWH2F  ***\n",$time, i);
  Addr = 16+ (i*1<<AXI4_BYTES_4);
  wr_resp_tr = `lwh2f_test_m.manager_bfm_wr_tx( (4+i), Addr );	// id, addr
  wr_resp_tr.set_burst_length(3); 
  wr_resp_tr.set_size(AXI4_BYTES_4); 
  wr_resp_tr.set_burst_type(BURST_TYPE_INCR); 
  wr_resp_tr.set_data_words(Data[0], 0);	// data, id
  wr_resp_tr.set_data_words(Data[1], 1); 
  wr_resp_tr.set_data_words(Data[2], 2); 
  wr_resp_tr.set_data_words(Data[3], 3); 
  wr_resp_tr.set_write_strobes(4'hf, 0);	// strobe, id
  wr_resp_tr.set_write_strobes(4'hf, 1); 
  wr_resp_tr.set_write_strobes(4'hf, 2); 
  wr_resp_tr.set_write_strobes(4'hf, 3); 
  `lwh2f_test_m.put_transaction(wr_resp_tr);
  `lwh2f_test_m.drive_transaction();

  rd_resp_tr = `lwh2f_test_m.manager_bfm_rd_tx( (4+i), Addr );	// id, addr
  rd_resp_tr.set_burst_length(3); 
  rd_resp_tr.set_size(AXI4_BYTES_4); 
  rd_resp_tr.set_burst_type(BURST_TYPE_INCR); 

fork 
   begin 
	`lwh2f_test_m.put_transaction(rd_resp_tr); 
	`lwh2f_test_m.drive_transaction(); 
   end 
   begin 
	`lwh2f_test_m.put_transaction(wr_resp_tr); 
	`lwh2f_test_m.drive_transaction(); 
   end 
join 

   for (j=0; j<4; j++) begin
     if (rd_resp_tr.get_data_words(j) == Data[j]) begin
       f_incr[i][j]=1'b1;
       $display ( "@ %t  Read correct data (%h) at address (%h)",
       		$time, Data[j], (Addr + j) );             
       end 
    else
       $display ( "@ %t  Error: Expected data (%h) at address (%h), but got %h",
       		$time, Data[j], (Addr + j), rd_resp_tr.get_data_words(j));
    end	   //for j loop
end	//for i loop
///////////////////////////////////// CHECK TESTS        //////////////////////////
#(5000000 - $time)		// wait until a certain time

status=1'b1;	//assume pass
for (i = 0; i < 4; i++)
   if (f_rw[i]!=1'b1)
	status=1'b0;

for (i=0; i<4; i++)
   for (j=0; j<2; j++)
      	if (f_incr[i][j]!=1'b1)
      		status=1'b0;	
	
if (status==1'b1)
  $display ("\n\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> pass    LWH2F ");
else begin
  $display ("\n\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> fail    LWH2F ");
  for (i=0; i<4; i++)
    for (j=0; j<2; j++)
      $display (">> f_rw[%d] is %b  >> f_incr[%d][%d] is %b ",
      		i, f_rw[i], i, j, f_incr[i][j] );
end

$display("\n@%0t*********** END OF TEST *********      LWH2F    ******\n",$time);

end     // initial begin
endmodule
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