Agilex™ 7 Hard Processor System Component Reference Manual
ID
683581
Date
10/08/2025
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the Agilex™ 7 HPS Component Revision History
2.1. Parameterizing the HPS Component
- Install the current version of the Quartus® Prime Pro Edition design software, along with Agilex™ 7 device support.
Instructions on how to install the current version are located at the FPGA Software Download Center webpage.
- Open the Quartus® Prime software.
Figure 1. Quartus® Prime Starting Screen
- Open Platform Designer by selecting Tools > Platform Designer .
Figure 2. Select Platform Designer
- Select an existing Quartus® Prime project and Platform Designer system or create new files. Ensure that Agilex™ 7 device is selected in the Device Family dropdown, and an appropriate device is selected in the Device Part dropdown.
Figure 3. Select or Create Files
- In the IP Catalog tab, under Library, select Processors and Peripherals > Hard Processor Systems > Hard Processor System Agilex™ 7 FPGA IP.
Figure 4. Platform Designer IP Catalog