Agilex™ 7 Hard Processor System Component Reference Manual

ID 683581
Date 10/08/2025
Public
Document Table of Contents

3.3. FPGA-to-HPS AXI* Slave Interface

The FPGA‑to‑HPS AXI* slave interface, f2h_axi_slave, is connected to a Mentor Graphics® AXI* slave BFM for simulation with an instance name of f2h_axi_slave_inst. Platform Designer configures the BFM as shown in the following table. The BFM clock input is connected to f2h_axi_clock clock.

Table 15.  Configuration of FPGA-to-HPS AXI* Slave BFM
Parameter Value
AXI* Address Width 20–37
AXI* Read Data Width 128
AXI* Write Data Width 128
AXI* ID Width 4

You control and monitor the AXI* slave BFM by using the BFM API.