Agilex™ 7 Hard Processor System Component Reference Manual
ID
683581
Date
10/08/2025
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the Agilex™ 7 HPS Component Revision History
3. Simulating the Agilex™ 7 HPS Component
Altera® provides Bus Functional Models (BFM) to simulate the AXI* interfaces of Agilex™ 7.
Simulator Support | Level |
---|---|
Aldec Riviera-PRO* | Full |
Cadence Xcelium* Parallel Simulator | Full |
Siemens EDA QuestaSIM* Simulator1 | Full |
Synopsys* VCS* , VCS* MX | Full |
For more information, refer to the Altera® AXI4 Bus Functional Model User Guides.
Section Content
Simulation Flows
Clock and Reset Interfaces
FPGA-to-HPS AXI Slave Interface
HPS-to-FPGA AXI Master Interface
Lightweight HPS-to-FPGA AXI Master Interface
HPS-to-FPGA MPU Event Interface
Interrupts Interface
HPS-to-FPGA Debug APB Interface
FPGA-to-HPS System Trace Macrocell Hardware Event Interface
HPS-to-FPGA Cross-Trigger Interface
HPS-to-FPGA Trace Port Interface
FPGA-to-HPS DMA Handshake Interface
General Purpose Input Interface
EMIF Conduit
Simulating the Agilex 7 HPS Component Revision History
Related Information
1 QuestaSim is the generic name for Questa Core and Questa Prime simulators from Siemens EDA.