Agilex™ 7 Hard Processor System Component Reference Manual
ID
683581
Date
10/08/2025
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the Agilex™ 7 HPS Component Revision History
4.1. Setting up the HPS Component for Simulation
Follow these steps to set up the HPS component for simulation.
- Add the HPS component from the Platform Designer Component Library.
- Configure the HPS component based on your application needs by selecting or deselecting the HPS/FPGA interfaces.
- Connect the appropriate HPS interfaces to other components in the system. For example, connect:
- the h2f_axi_master AXI* 4 manager interface to an On-Chip Memory II (RAM or ROM) IP component
- the h2f_lw_axi_master AXI* 4 manager interface to an On-Chip Memory II (RAM or ROM) component
- For this example, name the project simple. The Platform Designer connections are shown below.
Figure 38. Platform Designer Connections
- This example uses the LWH2F bridge with 32-bit width and the H2F bridge with 128-bit width. The F2H bridge is not used. The parameters are shown below.
Figure 39. HPS FPGA Bridges Parameters
- This example uses two On-Chip Memory II (RAM or ROM) IP components, one for the h2f_lw_axi_master interface and one for the h2f_axi_master interface.
- The one connected to the h2f_lw_axi_master has an Interface type of AXI* -4, a data width of 32-bits, and Transaction ID width of 4.
- The one connected to the h2f_axi_master has an Interface type of AXI* -4, a data width of 128-bits, and Transaction ID width of 4. Refer to the parameter GUI below.
Figure 40. On-Chip Memory II (RAM or ROM) IP Parameter GUI