Agilex™ 7 Hard Processor System Component Reference Manual

ID 683581
Date 10/08/2025
Public
Document Table of Contents

2.4.1. Debugging HPS EMIF with the EMIF Debug Toolkit

For Agilex™ 7 M-series devices (excluding Agilex™ 7 F-Series and I-Series), the HPS EMIF controller supports the External Memory Interface Debug Toolkit. Follow these steps to create a design that instantiates the FPGA memory controller using the HPS memory interface parameters and routes it to the same I/O used by the HPS EMIF.
  1. Select the HPS EMIF IP within the Platform Designer project.
  2. Click Dive Into Packaged Subsystem in the External Memory Interfaces for HPS window.
    Figure 23. Dive Into Packaged Subsystem
  3. 3. In the new window, click the EMIF IP inside of the packaged IP window to view the Memory Device parameters on the right side, then click Generate Example Design.
    Figure 24. Generate Example Design
  4. Select the directory for the compile design.
    Figure 25. Select Example Design Directory
  5. The example design is created.
    Figure 26. Example Design Completed
  6. Save and exit the Dive Into Packaged Subsystem window.