Agilex™ 7 Hard Processor System Component Reference Manual
ID
683581
Date
10/08/2025
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the Agilex™ 7 HPS Component Revision History
2.4.1. Debugging HPS EMIF with the EMIF Debug Toolkit
For Agilex™ 7 M-series devices (excluding Agilex™ 7 F-Series and I-Series), the HPS EMIF controller supports the External Memory Interface Debug Toolkit. Follow these steps to create a design that instantiates the FPGA memory controller using the HPS memory interface parameters and routes it to the same I/O used by the HPS EMIF.
- Select the HPS EMIF IP within the Platform Designer project.
- Click Dive Into Packaged Subsystem in the External Memory Interfaces for HPS window.
Figure 23. Dive Into Packaged Subsystem
- 3. In the new window, click the EMIF IP inside of the packaged IP window to view the Memory Device parameters on the right side, then click Generate Example Design.
Figure 24. Generate Example Design
- Select the directory for the compile design.
Figure 25. Select Example Design Directory
- The example design is created.
Figure 26. Example Design Completed
- Save and exit the Dive Into Packaged Subsystem window.