Agilex™ 7 Hard Processor System Component Reference Manual
ID
683581
Date
10/08/2025
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the Agilex™ 7 HPS Component Revision History
3.1.3.2. Cadence® Xcelium* Simulation Steps
- Locate your top-level simulation model, TopLevel.v or TopLevel.vhdl, which you have created.
- Locate it at <project directory>/<Platform Designer design name>/sim/.
- In this directory, name the file as TopLevel.v and TopLevel.vhdl that was created when you previously click the Generate button.
- Locate the xcelium_setup.sh script and execute the simulator in the <project directory>/<Platform Designer design name>/sim/xcelium/.
- Create a new file my_xcelium_setup.sh and write the following content to the file.
xmvlog <compilation options> <design and testbench files> # example: xmvlog ../TopLevel.v source <path_to>/xcelium_setup.sh \ SKIP_ELAB=0 \ SKIP_SIM=0 \ SKIP_FILE_COPY=0 \ SKIP_DEV_COM=0 \ SKIP_COM=0 \ TOP_LEVEL_NAME=<”top_level_name”> \ # example: TOP_LEVEL_NAME=“TopLevel” \ USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ns" \ USER_DEFINED_SIM_OPTIONS="" \ # example: USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
- Set up your developer environment with the proper resources. The Cadence® Xcelium* simulator requires an end user proprietary license.
- Run the simulation script to start simulation runtime.
sh my_xcelium_setup.sh
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