Agilex™ 7 Hard Processor System Component Reference Manual
ID
683581
Date
10/08/2025
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the Agilex™ 7 HPS Component Revision History
3.1.3.5. VSIM Command Line Aliases and Variables
Command Line Aliases | Description |
---|---|
dev_com | Compile device library files. |
com | Compile the design files in correct order. |
elab | Elaborate top level design. |
elab_debug | Elaborate the top level design with -dbg -O2 option. |
ld | Compile all the design files and elaborate the top level design. |
ld_debug | Compile all the design files and elaborate the top level design with -dbg -O2 option. |
Variables | Description |
---|---|
TOP_LEVEL_NAME | Top level module name. |
QSYS_SIMDIR | Platform Designer base simulation directory. |
QUARTUS_INSTALL_DIR | Quartus installation directory. |
USER_DEFINED_COMPILE_OPTIONS | User-defined compile options, added to com/dev_com aliases. |
USER_DEFINED_VHDL_COMPILE_OPTIONS | User-defined vhdl compile options, added to com/dev_com aliases. |
USER_DEFINED_VERILOG_COMPILE_OPTIONS | User-defined verilog compile options, added to com/dev_com aliases. |
USER_DEFINED_ELAB_OPTIONS | User-defined elaboration options, added to elab/elab_debug aliases. |