Agilex™ 7 Hard Processor System Component Reference Manual
ID
683581
Date
10/08/2025
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the Agilex™ 7 HPS Component Revision History
3.1.3.4. Riviera-PRO* Simulation Steps
- Locate your top-level simulation model, TopLevel.v or TopLevel.vhdl, which you have created.
- Locate the rivierapro_setup.tcl script and execute the simulator in the <project directory>/<Platform Designer design name>/sim/aldec/.
- Create a new file my_rivierapro_setup.do and write the following content to the file.
source <path_to>/rivierapro_setup.tcl dev_com com vlog <compilation_options> <design_top_level_vfile> # example: vlog -timescale 1ps/1ps ../TopLevel.v set TOP_LEVEL_NAME <design_top_level_name> # example: set TOP_LEVEL_NAME TopLevel set USER_DEFINED_ELAB_OPTIONS <elaboration options> (optional) elab run -a exit -code 0 (optional)
Refer to VSIM Command Line Aliases and Variables for more information about the vsim aliases and variables. - Set up your developer environment with the proper resources. The Riviera-PRO* simulator requires an end user proprietary license.
- Run the simulation script to start simulation runtime.
vsim -do my_rivierapro_script.do
Since no testbench is added, it only shows that all the HPS IP simulation files were successfully compiled and elaborated.