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1. Getting Started
2. Development Kit Overview
3. Power Up the Development Kit
4. Board Test System (BTS)
5. Development Kit Hardware and Configuration
6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide
A. Development Kit Components
B. Safety and Regulatory Information
C. Compliance and Conformity Information
A.1. Components Overview
A.2. Power, Thermal, and Mechanical Considerations
A.3. Clock Circuits
A.4. Memory Interface
A.5. PCIe Interface
A.6. UPI Interface
A.7. Transceiver Signals: PCIe and UPI Interface
A.8. SlimSAS Connector
A.9. QSFP Network Interface
A.10. I2C Interface
A.11. QSPI Flash Memory
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5.3.2. JTAG Mode
The JTAG Switch implemented in the Intel® MAX® 10 System Control (U11) allows the selection of the device(s) to be included in the JTAG chain. It is done by the settings of the DIP switch SW33. The embedded Intel® FPGA Download Cable (or external Intel® FPGA Download Cable) or PCIe* JTAG can be selected as the source for programming the device(s) on the chain. The embedded Intel® FPGA Download Cable is the default setting for this configuration mode.
Figure 29. JTAG Chain
The on-board Intel® FPGA Download Cable is implemented in a Intel® MAX® 10 device. A micro-USB connector connecting to a CY7C68013A USB2 PHY provides the data to Intel® MAX® 10 device. This allows you to configure the FPGA using a USB cable, which is directly connected to a host PC running Intel® Quartus® Prime Pro Edition software without requiring the external Intel® FPGA Download Cable.
You can also use the external Intel® FPGA Download Cable on J2 to configure the FPGA.