Intel® Stratix® 10 DX FPGA Development Kit User Guide

Download PDF
ID 683561
Date 9/25/2023
Public
Document Table of Contents
Document Table of Contents x
1. Getting Started 2. Development Kit Overview 3. Power Up the Development Kit 4. Board Test System (BTS) 5. Development Kit Hardware and Configuration 6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide A. Development Kit Components B. Safety and Regulatory Information C. Compliance and Conformity Information
1. Getting Started x
1.1. About this Document 1.2. Installing the Intel® Quartus® Prime Pro Edition Software 1.3. Downloading the Board Package 1.4. Installing the Driver for Intel FPGA Download Cable II
1.2. Installing the Intel® Quartus® Prime Pro Edition Software x
1.2.1. Activating Your License
2. Development Kit Overview x
2.1. Supported Features 2.2. Recommended Operating Conditions 2.3. Handling the Board
3. Power Up the Development Kit x
3.1. Default Switch Settings 3.2. Connectors and LEDs 3.3. Performing Board Restore through Board Test System (BTS) 3.4. Controlling On-board Clock
4. Board Test System (BTS) x
4.1. Preparing the Development Kit 4.2. Running the Board Test System 4.3. Using the Board Test System 4.4. Smart VID Setting
4.3. Using the Board Test System x
4.3.1. Configure Menu 4.3.2. Sys Info Tab 4.3.3. GPIO Tab 4.3.4. QSFP Tab 4.3.5. Component DDR4 CH0 Tab 4.3.6. Component DDR4 CH1 Tab 4.3.7. DDR4 DIMM CH0 Tab 4.3.8. DDR4 DIMM CH1 Tab 4.3.9. Power Monitor 4.3.10. Clock Controller
5. Development Kit Hardware and Configuration x
5.1. FPGA Configuration 5.2. Programming the FPGA Over Intel® FPGA Download Cable 5.3. Configuration Modes
5.3. Configuration Modes x
5.3.1. Avalon® Streaming Interface x8 Mode 5.3.2. JTAG Mode
5.3.1. Avalon® Streaming Interface x8 Mode x
Avalon® Streaming Interface x8 Configuration Guideline
A. Development Kit Components x
A.1. Components Overview A.2. Power, Thermal, and Mechanical Considerations A.3. Clock Circuits A.4. Memory Interface A.5. PCIe Interface A.6. UPI Interface A.7. Transceiver Signals: PCIe and UPI Interface A.8. SlimSAS Connector A.9. QSFP Network Interface A.10. I2C Interface A.11. QSPI Flash Memory
A.2. Power, Thermal, and Mechanical Considerations x
A.2.1. Power Guidelines A.2.2. Thermal Requirements A.2.3. Mechanical Requirements
A.2.1. Power Guidelines x
A.2.1.1. Power Distribution A.2.1.2. Power Sequence A.2.1.3. Power Measurement
A.2.2. Thermal Requirements x
A.2.2.1. Operating Conditions A.2.2.2. Temperature Monitoring
A.9. QSFP Network Interface x
A.9.1. Dual Port Controller
A.11. QSPI Flash Memory x
A.11.1. Configuration QSPI Flash Memory A.11.2. NIOS QSPI Flash Memory
B. Safety and Regulatory Information x
B.1. Safety Warnings B.2. Safety Cautions
1. Getting Started
2. Development Kit Overview
3. Power Up the Development Kit
4. Board Test System (BTS)
5. Development Kit Hardware and Configuration
6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide
A. Development Kit Components
B. Safety and Regulatory Information
C. Compliance and Conformity Information

A.1. Components Overview

Table 8.   Intel® Stratix® 10 DX FPGA Development Kit Components
Board Reference Component Description
Featured Devices
U1 Intel® Stratix® 10 DX FPGA
  • Logic elements: 2.8M
  • DSP blocks: 5760
  • M20K memory blocks: 11721
  • Package type: 2912 BGA
  • Transceiver count: 84
    • 4x P-Tile supporting PCIe X16 Gen4 (16 Gb/s) or UPI X 20 (1up to 11.2 GT/s)
    • 1x E-Tile transceiver supporting 2x 56Gbps PAM4 or 4x 25Gbps NRZ
U11 Intel® MAX® 10
  • Logic elements: 50K
  • Package type: 256 FBGA
  • 1.8V VCCINT
Clock Circuits
X4 Intel® MAX® 10 Reference Clock The crystal oscillator provides the reference clock for Intel® MAX® 10 device:
  • Out= 125.00 MHz
U7 Programmable Clock Generator Si5332A Default frequencies:
  • Out0 = 100.00 MHz
  • Out1 = 125.00 MHz
  • Out2 = 133.333MHz
  • Out3 = 133.333MHz
  • Out4 = 133.333 MHz
  • Out5 = 133.333MHz
  • Out6 = 100.00 MHz
  • Out7 = 100.00MHz
U9 Programmable Clock Generator Si5391A Default frequencies:
  • CLK0 = 156.25MHz
  • CLK0A = 156.25 MHz
  • CLK1 = 312.50 MHz
  • CLK2 = 312.50 MHz
  • CLK3 = 312.50 MHz
  • CLK4 = Not used
  • CLK5 = Not used
  • CLK6 = 100.00 MHz
  • CLK7 = 100.00 MHz
  • CLK8 = 100.00 MHz
  • CLK9 = 100.00 MHz
  • CLK9A = 100.00 MHz
Transceiver Interfaces
J9 PCIe x16 gold fingers PCIe TX/RX x16 interface from FPGA P-tile 10A
J38 PCIe x16 or UPI x20, Link 1 PCIe/UPI Transmit interface from FPGA P-tile 11B
J40 PCIe x16 or UPI x20, Link 1 PCIe/UPI Receive interface from FPGA P-tile 11B
J39 PCIe x16 or UPI x20, Link 2 PCIe/UPI Transmit interface from FPGA P-tile 11C
J41 PCIe x16 or UPI x20, Link 2 PCIe/UPI Receive interface from FPGA P-tile 11C
J55 PCIe x16 or UPI x20, Link 0 PCIe/UPI Transmit interface from FPGA P-tile 10B
J65 PCIe x16 or UPI x20, Link 0 PCIe/UPI Receive interface from FPGA P-tile 10B
J15 QSFP 1 connector Four TX/RX channels from FPGA Bank 4F
J18 QSFP 2 connector Four TX/RX channels from FPGA Bank 4F
General User Input/Output
D9, D10, D14, D15 User defined LEDs Four green-color user LEDs. Illuminates when driven low
Memory
J73 DDR4 x72 DIMM connector One X72 memory interface supporting DDR4 (x72) or Intel Optane® DC Persistent memory module:
  • DDR4 memory (x72) 1333 MHz
  • Intel Optane® DC Persistent memory (requires memory controller IP core)
J74 DDR4 x72 DIMM connector One X72 memory interface supporting DDR4 (x72) or Intel Optane® DC Persistent memory module:
  • DDR4 memory (x72) 1333 MHz
  • Intel Optane® DC Persistent memory (requires memory controller IP core)
U142, U143, U144, U145, U146 On-board DDR4 x72 Memory interface This on-board DDR4 x72 memory supports 8 GB at up to 1200 MHz
U152, U153, U154, U155, U156 On-board DDR4 x72 Memory interface This on-board DDR4 x72 memory supports 8 GB at up to 1200 MHz
U41 NIOS Flash 64K-bit This on-board Flash is for Intel® MAX® 10
U66 QSPI 2 Gbit NOR Flash This on-board Flash is for image storage for FPGA
Communication Ports
J9 PCI Express x16 edge connector Gold-plated edge fingers for up to x16 signaling in either Gen1, Gen2, Gen3, or Gen4 mode
J15 QSFP 1 Interface Provides four transceiver channels for a 100G QSFP module
J18 QSFP 2 Interface Provides four transceiver channels for a 100G QSFP module
J97 I2C/PMBus connector For accessing core power controller
J17 I2C connector For cccessing the I2C1 bus
J2 External JTAG Port This port allows the use of Intel® FPGA Download Cable II dongle to access the JTAG links on the board. Connection to this port automatically disables the internal Intel FPGA Download Cable II JTAG.
CN1 Micro-USB connector Embedded Intel Intel FPGA Download Cable II JTAG for programming the FPGA via USB cable.
Power Supply
J9 PCI Express edge connector Interfaces to a PCI Express root port such as an appropriate PC motherboard for 12V power source
J42 DC input jack Accepts a 12 V DC power supply when powering the board from the provided power brick for lab bench operation.

When operating from the PCIe slot, this input must also be connected to the 8-pin Aux PCIe power connector provided by the PC system along with J42, or else the board will not power on.

SW31 Power switch Switch to power ON or OFF the board when supplied from the DC input jack
U217 12V Hot Swap Controller Provide protection for AUX power input (J42)
U96 12V Hot Swap Controller Provide protection for PCIe slot power input (J9)
U93 Controlled power FET Perform power bridging function between AUX2 and PCIe slot when the board is not used in PCIe system
U101 3.3V Voltage regulator Provides 3.3V to power system
U99 5V Voltage regulator Provides 5V to power system
U47,U240,U77,U241,U242 4-phase VCC Core Voltage regulator Provides power to VCC core of Intel® Stratix® 10 FPGA
U230 0.9V Voltage regulator Provides power to all power rails in Group 1
U113 1.8V Voltage regulator Provides power to VCCPT and other rails in Group 2
U186 1.8V Voltage regulator Provides power to VCCH and VCCCLK for P-tiles
U184 1.1V Voltage regulator Provides power to VCCH for E-tile
U78 2.5V Voltage regulator Provides power to VCCCLK for E-tile
U76 2.4V Voltage regulator Provides power to VCCFUSEWR_SDM of Intel® Stratix® 10 FPGA
U188 1.8V Voltage regulator Provides power to VCCIO of Intel® Stratix® 10 FPGA
U116 1.2V and 2.5V Voltage regulator Provides power to Intel® MAX® 10 core and other rails
U79 1.8V Voltage regulator Provides power to VCCIO of Intel® MAX® 10
U163 2.5V Voltage regulator Provides power to DDR4 Channel 0
U164 0.6V Voltage regulator Provides power to DDR4 VTT Channel 0
U159 1.2V Voltage regulator Provides power to DDR4 Channel 0
U165 2.5V Voltage regulator Provides power to DDR4 Channel 1
U166 0.6V Voltage regulator Provides power to DDR4 VTT Channel 1
U157 1.2V Voltage regulator Provides power to DDR4 Channel 1
U192, U193 0.6V Precision voltage reference Provides reference voltage to DDR4 Channel 0 and Channel 1
U136 Controlled power FET Control power to all memory voltage regulators
U51 Power protector Provides power protection to QSFP 1 (J16)
U52 Power protector Provides power protection to QSFP 2 (J18)
Level Two Title