Intel® Stratix® 10 DX FPGA Development Kit User Guide

ID 683561
Date 9/25/2023
Document Table of Contents

A.11.1. Configuration QSPI Flash Memory

The Intel® Stratix® 10 DX FPGA Development Kit has one 2-Gbit QSPI flash device for non-volatile storage of the FPGA configuration data, board information, test application data and user code space.

The flash device is implemented to achieve a 4-bit wide data bus. Only Intel® MAX® 10 CPLD can access this flash device. The Intel® MAX® 10 CPLD accesses are for AVST x8 configuration of the FPGA at power-on and board reset events. It uses the Parallel Flash Loader (PFL) II IP core.
Table 13.  Memory Map of the QSPI 2G Flash
Block Access Size Address
Reserved RW 17,920 KB 0x510.0000 - FFF.FFFF
Factory image RW 81,920 KB 0x010.0000 - 50F.FFFF
PFL Option bits RW 960 KB 0x001.0000 - 00F.FFFF
Reserved RW 64 KB 0x000.0000 - 000.FFFF