Intel® Stratix® 10 DX FPGA Development Kit User Guide

ID 683561
Date 9/25/2023
Document Table of Contents

4.3.5. Component DDR4 CH0 Tab

This tab allows you to read and write Component DDR4 CH0 memory on your board.

Figure 13. Component DDR4 CH0 Tab

The following sections describe the controls on the Component DDR4 CH0 tab:


Initiates DDR4 memory transaction performance analysis.


Terminates transaction performance analysis.

Performance Indicator

These controls display current transaction performance analysis information collected since you last clicked Start:
  • Write, Read and Total performance bars: Shows the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
  • Write (MBps), Read (MBps) and Total (MBps): Shows the number of bytes analyzed per second.
  • Data Bus: 72-bits (8-bits ECC) wide and the frequency is 1066 MHz double data rate. 2133 Mbps per pin. Equating to a theoretical maximum banwidth of 136,512 Mbps or 17,064 MBps.

Error Control

This control displays data errors detected during analysis and allows you to insert errors:
  • Detected errors: Displays the number of data errors detected in the hardware.
  • Inserted errors: Displays the number of errors inserted into the transaction stream.
  • Insert: Inserts a one-word error into the transaction stream each time you click the button. Insert error is only enabled during transaction performance analysis.
  • Clear: Resets the detected error and inserted error counters to zero.

Address Range

Determines the number of addresses to use in each iteration of reads and writes.