1. Getting Started
2. Development Kit Overview
3. Power Up the Development Kit
4. Board Test System (BTS)
5. Development Kit Hardware and Configuration
6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide
A. Development Kit Components
B. Safety and Regulatory Information
C. Compliance and Conformity Information
A.1. Components Overview
A.2. Power, Thermal, and Mechanical Considerations
A.3. Clock Circuits
A.4. Memory Interface
A.5. PCIe Interface
A.6. UPI Interface
A.7. Transceiver Signals: PCIe and UPI Interface
A.8. SlimSAS Connector
A.9. QSFP Network Interface
A.10. I2C Interface
A.11. QSPI Flash Memory
A.6. UPI Interface
The Intel® Stratix® 10 DX FPGA Development Kit supports three individual UPI interfaces. The UPI functionality is enabled by a combination of the appropriate P-Tile settings and UPI protocol IP core available in Intel® Quartus® Prime Pro Edition software (additional licensing and enablement may apply). Each interface consists of two SlimSAS connectors, one for transmit signals and one for receive signals. Each UPI interface provides node ID for the host CPU to identify. Node ID can be set by strapping resistors on the board.
The Slim SAS connectors also carry SMBus/I2C, clock, GPIO, and PCIe signals.