Intel® Stratix® 10 DX FPGA Development Kit User Guide

ID 683561
Date 9/25/2023
Public
Document Table of Contents

A.8. SlimSAS Connector

Each PCIe or UPI interface connects to two slim SAS connectors, one for transmit signals and one for receive signals. Cables are used to connect the UPI or PCIe links from the devkit to the host board.

For UPI interface:
  • UPI 0 Link, P-tile (10B) is routed to J55(FPGA-to-CPU) and J65(CPU-to-FPGA)
  • UPI 1 Link, P-tile (11B) is routed to J38(FPGA-to-CPU) and J40(CPU-to-FPGA)
  • UPI 2 Link, P-tile (11C) is routed to J39(FPGA-to-CPU) and J41(CPU-to-FPGA)
Figure 46. SlimSAS Connector Pinout