Intel® Stratix® 10 DX FPGA Development Kit User Guide

Download PDF
ID 683561
Date 9/25/2023
Public
Document Table of Contents
Document Table of Contents x
1. Getting Started 2. Development Kit Overview 3. Power Up the Development Kit 4. Board Test System (BTS) 5. Development Kit Hardware and Configuration 6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide A. Development Kit Components B. Safety and Regulatory Information C. Compliance and Conformity Information
1. Getting Started x
1.1. About this Document 1.2. Installing the Intel® Quartus® Prime Pro Edition Software 1.3. Downloading the Board Package 1.4. Installing the Driver for Intel FPGA Download Cable II
1.2. Installing the Intel® Quartus® Prime Pro Edition Software x
1.2.1. Activating Your License
2. Development Kit Overview x
2.1. Supported Features 2.2. Recommended Operating Conditions 2.3. Handling the Board
3. Power Up the Development Kit x
3.1. Default Switch Settings 3.2. Connectors and LEDs 3.3. Performing Board Restore through Board Test System (BTS) 3.4. Controlling On-board Clock
4. Board Test System (BTS) x
4.1. Preparing the Development Kit 4.2. Running the Board Test System 4.3. Using the Board Test System 4.4. Smart VID Setting
4.3. Using the Board Test System x
4.3.1. Configure Menu 4.3.2. Sys Info Tab 4.3.3. GPIO Tab 4.3.4. QSFP Tab 4.3.5. Component DDR4 CH0 Tab 4.3.6. Component DDR4 CH1 Tab 4.3.7. DDR4 DIMM CH0 Tab 4.3.8. DDR4 DIMM CH1 Tab 4.3.9. Power Monitor 4.3.10. Clock Controller
5. Development Kit Hardware and Configuration x
5.1. FPGA Configuration 5.2. Programming the FPGA Over Intel® FPGA Download Cable 5.3. Configuration Modes
5.3. Configuration Modes x
5.3.1. Avalon® Streaming Interface x8 Mode 5.3.2. JTAG Mode
5.3.1. Avalon® Streaming Interface x8 Mode x
Avalon® Streaming Interface x8 Configuration Guideline
A. Development Kit Components x
A.1. Components Overview A.2. Power, Thermal, and Mechanical Considerations A.3. Clock Circuits A.4. Memory Interface A.5. PCIe Interface A.6. UPI Interface A.7. Transceiver Signals: PCIe and UPI Interface A.8. SlimSAS Connector A.9. QSFP Network Interface A.10. I2C Interface A.11. QSPI Flash Memory
A.2. Power, Thermal, and Mechanical Considerations x
A.2.1. Power Guidelines A.2.2. Thermal Requirements A.2.3. Mechanical Requirements
A.2.1. Power Guidelines x
A.2.1.1. Power Distribution A.2.1.2. Power Sequence A.2.1.3. Power Measurement
A.2.2. Thermal Requirements x
A.2.2.1. Operating Conditions A.2.2.2. Temperature Monitoring
A.9. QSFP Network Interface x
A.9.1. Dual Port Controller
A.11. QSPI Flash Memory x
A.11.1. Configuration QSPI Flash Memory A.11.2. NIOS QSPI Flash Memory
B. Safety and Regulatory Information x
B.1. Safety Warnings B.2. Safety Cautions
1. Getting Started
2. Development Kit Overview
3. Power Up the Development Kit
4. Board Test System (BTS)
5. Development Kit Hardware and Configuration
6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide
A. Development Kit Components
B. Safety and Regulatory Information
C. Compliance and Conformity Information

3.2. Connectors and LEDs

Figure 4. Location of Connectors and LEDs
Table 6.  Connectors
Connector Description
J2 External JTAG connector For use with Intel® FPGA Download Cable
J42 AUX Power connector For external 12V AUX power supply or power adapter
J97 I2C/PMBus connector For accessing the core power controller
J17 I2C connector To access I2C bus
J15 QSFP 1 connector For using the QSFP interface
J18 QSFP 2 connector
CN1 USB connector For programming FPGA using on-board Intel® FPGA Download Cable
J73 DIMM 0 connector For DDR4/DDR-T memory channel 0
J74 DIMM 1 connector For DDR4/DDR-T memory channel 1
J9 PCIe x16 Gold Finger For using the PCIe interface
J38 UPI 1 Transmit For UPI Link 1 connection from FPGA to CPU
J40 UPI 1 Receive For UPI Link 1 connection from CPU to FPGA
J39 UPI 2 Transmit For UPI Link 2 connection from FPGA to CPU
J41 UPI 2 Receive For UPI Link 2 connection from CPU to FPGA
J55 UPI 0 Transmit For UPI Link 0 connection from FPGA to CPU
J65 UPI 0 Receive For UPI Link 0 connection from CPU to FPGA
J24 Fan connector For connecting to the heatsink cooling fan
Table 7.  LEDs
LEDs Description
D18 QSFP 1 Link LED for 25G Green LED:
  • ON: link
  • Blinks: Activities
D20 QSFP 1 Link LED for 10G Yellow LED:
  • ON: link
  • Blinks: Activities
D22 QSFP 2 Link LED for 25G Green LED:
  • ON: link
  • Blinks: Activities
D21 QSFP 2 Link LED for 10G Yellow LED:
  • ON: link
  • Blinks: Activities
D9 USER LED 0 Green LED for USER LED 0
D10 USER LED 1 Green LED for USER LED 1
D14 USER LED 2 Green LED for USER LED 2
D15 USER LED 3 Green LED for USER LED 3
D56 POWER GOOD LED Yellow LED:
  • ON: All power is good
  • OFF: Power failure
D57 CONFIG DONE LED
Green LED:
  • ON: FPGA configuration successful
  • OFF: FPGA configuration failed
D13 MAX10 CONFIG DONE LED
Green LED:
  • ON: MAX10 configuration successful
  • OFF: MAX10 configuration failed
D40 Over Temp LED Red LED:
  • ON:
  • OFF:
D53 POWER LED
Blue LED:
  • ON: Devkit power is on
  • OFF: Devkit power is off
Level Two Title