Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683532
Date 8/05/2019
Document Table of Contents Unified Data Interface in 40GBASE-SR4 Mode

Each lane of the 40GbE PCS PHY data interface is striped across 128-bit segments of the unified data interface transmit and receive data ports. Each 40-bit PCS PHY data lane is mapped to the lower 40 bits of the 128-bit segment. The upper 88 bits of the transmit datapath segment should be statically driven low. The upper 88 bits of the receive datapath segment should be left unconnected.

The unified data interface’s transmit and receive control ports are not utilized in 40GBASE-SR4 mode. Statically drive the a2f_tx_control port low and leave f2a_rx_control unconnected.

Flow control is utilized in 40GBASE-SR4 mode between the 40GbE PCS and HSSI PHY PMA layers. See the HSSI Unified Data Interface section for details about the flow control signaling.