Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683532
Date 8/05/2019
Document Table of Contents Receiver CTLE AC Gain sysfs Encodings

analog-pma-setting-index = "0"

HSSI PHY receiver CTLE AC Gain is specified using the XCVR_A10_RX_ADP_CTLE_ACGAIN_4S parameter. The following table shows the supported range of values for receiver CTLE AC Gain with the corresponding sysfs analog-pma-setting hex string value.

Table 14.  Receiver CTLE AC Gain sysfs Value Encodings
XCVR_A10_RX_ADP_CTLE_ACGAIN_4S analog-pma-setting

RADP_CTLE_ACGAIN_4S_ <0 to 28>

Range of string values from "0" to "1c" (default = "0")