Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683532
Date 8/05/2019
Document Table of Contents

1.1. How to Use this Guide

There are two major components to enable using the network port feature on the Intel® PAC with Intel® Arria® 10 GX FPGA. First, the host must configure the HSSI PHY in the hardware platform’s FIM for one of the supported modes (4x10GBASE-SR or 40GBASE-SR4). Secondly, the host must load an accelerator function (AF) that supports the network port feature.

The AFU Design section covers the requirements in the AFU design to enable the network port feature. The section describes the network MAC and PHY components that must be implemented in the AFU design and how to connect them to the HSSI PHY in the FIM through the hssi device interface. This section also gives some guidance on verifying your AFU implementation for network port connectivity in hardware.

The OPAE Support section covers using the OPAE driver and tools to provision the network port feature from the host, including configuring the HSSI PHY for the desired mode of operation, loading a network-enabled AF, and retrieving information from the Intel® PAC with Intel® Arria® 10 GX FPGA such as MAC address.

This document was previously titled as HSSI User Guide for Intel Programmable Acceleration Card (PAC) Intel Arria 10 GX FPGA.