Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
ID
683532
Date
8/05/2019
Public
2.2.1.1. Clocks in 4x10GBASE-SR Mode
2.2.1.2. Unified Data Interface in 4x10GBASE-SR Mode
2.2.1.3. PHY Control and Status in 4x10GBASE-SR Mode
2.2.1.4. PR Management in 4x10GBASE-SR Mode
2.2.1.5. Reset Control and Status in 4x10GBASE-SR Mode
2.2.1.6. Initialization in 4x10GBASE-SR Mode
2.2.1.7. Unused 10GbE Channels
3.1.4.1. Receiver CTLE AC Gain sysfs Encodings
3.1.4.2. Receiver VGA sysfs Encodings
3.1.4.3. Receiver CTLE DC Gain sysfs Encodings
3.1.4.4. Transmitter Pre-Emphasis First Post Tap Encodings
3.1.4.5. Transmitter Pre-Emphasis Second Post Tap Encodings
3.1.4.6. Transmitter Pre-Emphasis First Pre Tap Encodings
3.1.4.7. Transmitter Pre-Emphasis Second Pre Tap Encodings
3.1.4.8. Transmitter VOD Encodings
3.2.2. Reading the Base MAC Address from the Intel® PAC with Intel® Arria® 10 GX FPGA
Each Intel® PAC with Intel® Arria® 10 GX FPGA reserves four consecutive MAC addresses. The Intel® PAC with Intel® Arria® 10 GX FPGA stores a single, universally unique base MAC address. For 4x10GBASE-SR mode, the Intel® PAC with Intel® Arria® 10 GX FPGA reserves the next three consecutive addresses.
Read the kernel driver eeprom sysfs file to retrieve the base MAC address as follows:
$ hexdump -C \ /sys/class/fpga/intel-fpga-dev.<i>/intel-fpga-fme.<j>/intel-pac-hssi.<m>.auto/hssi_mgmt/eeprom
The fields are delimited by LF (new line) characters. The base MAC address is located in the first field.