Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683532
Date 8/05/2019
Document Table of Contents PHY Control and Status in 40GBASE-SR4 Mode

Actively drive a2f_rx_set_locktoref and a2f_rx_set_locktodata and monitor f2a_rx_is_lockedtoref to control the HSSI PHY receive PMA CDRs lock sequence according to the HSSI Unified Data Interface section. The f2a_rx_enh_blk_lock and f2a_rx_enh_highber ports are not utilized in 40GBASE-SR4 mode – leave disconnected.