Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683532
Date 8/05/2019
Document Table of Contents Clocks in 4x10GBASE-SR Mode

The hssi interface provides a set of clocks and locked status flags to support the 10GbE MAC IP. The interface provides clock sources of 156.25MHz and 312.5MHz for both transmit and receive datapaths. The XGMII interface between the MAC and HSSI PHY is synchronous to f2a_tx_clk and f2a_rx_clk_ln0 for transmit and receive, respectively. The 312.5MHz clock sources and locked status outputs from the fPLLs in the HSSI PHY can be used by the MAC and related AFU logic as needed.