Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683532
Date 8/05/2019
Document Table of Contents

2.2.2. 40GBASE-SR4 Mode

In 40GBASE-SR4 mode, the AFU must implement a 40GbE PCS layer between the 40GbE MAC and HSSI PHY configured for 40GBASE-SR4 PMA-only mode. The interface between the 40GbE PCS implemented in the AFU and the HSSI PMA PHY is a 40-bit transmit and receive interface with flow control. The figure below and sections that follow describe how to connect 40GbE MAC/PCS-PHY IP to the HSSI PMA PHY over the hssi interface.

Figure 4. Connection to HSSI PHY in 40GBASE-SR4 Mode