Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683532
Date 8/05/2019
Document Table of Contents Reset Control and Status in 40GBASE-SR4 Mode

See the Resetting Transceiver Channels chapter in the Intel Arria 10 Transceiver PHY User Guide for details on using either the Intel Transceiver PHY Reset Controller IP included in Quartus Prime Pro or your own custom reset controller to properly sequence the resets for the serial transceiver blocks in the HSSI PHY. The above figure shows the use of a single controller for all transceiver lanes. The Intel Transceiver PHY Reset Controller IP can be configured for single or multi-lane use cases.