Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683532
Date 8/05/2019
Document Table of Contents

2. AFU Design

To enable the network port feature on the Intel® PAC with Intel® Arria® 10 GX FPGA, the AFU must implement the MAC and PHY IP blocks shown in the following table:

Table 1.  Required MAC and PHY IP Blocks

Network Port Mode

Required IP Blocks in the AFU



One 10GbE MAC per channel supported by the AFU (up to 4)



One 40GbE MAC

One 40GbE Physical Coding Sublayer (PCS) PHY

40GBASE-SR4 PMA-only

In addition to the above network IP blocks, the AFU must also implement the following supporting infrastructure:

  • Client-side data interfaces and DMA required to move data between host or local memory, AFU workload streams, and the network port
  • MMIO access through the cci-p device interface for host access to MAC/PHY control and status registers (CSRs), network statistics, and similar information

The FIM provides clock resources for client and PHY interfaces through the cci-p and hssi device interfaces.

The remainder of this section describes the hssi device interface and how to connect MAC and PHY IP implemented in the AFU to the HSSI PHY using the hssi interface.