Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683532
Date 8/05/2019
Document Table of Contents PR Management in 40GBASE-SR4 Mode

The f2a_prmgmt_ctrl_clk clock output is a 100MHz free running clock source that the MAC/PHY and related AFU logic can optionally use for miscellaneous lower speed logic. The 40GbE PCS layer should use the f2a_prmgmt_ram_ena output as a reset source.

The remaining ports on the PR management bus are for internal use in Intel® AFU example designs. Statically drive a2f_prmgmt_fatal_err and a2f_prmgmt_dout low.