Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683532
Date 8/05/2019
Document Table of Contents Reset Control and Status in 4x10GBASE-SR Mode

See the Resetting Transceiver Channels chapter in the Intel Arria 10 Transceiver PHY User Guide for details on using either the Intel Transceiver PHY Reset Controller IP included in Quartus Prime Pro or your own custom reset controller to properly sequence the resets for the serial transceiver blocks in the HSSI PHY. The Connection to HSSI PHY in 4x10GBASE-SR Mode figure in 4x10GBASE-SR Mode shows the use of a separate reset controller per channel, but you could also implement a single centralized reset controller for all channel transceivers. The Intel Transceiver PHY Reset Controller IP can be configured for single or multi-channel use cases.