Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 2/06/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

Note: All addresses in the programming sequence need to shift by a particular offset:
  • In case of x8, shift by 5 bits
  • In case of x16, shift by 6 bits
The MCDMA BAS programming sequence consists of the following steps:
  1. Allocate DMA-able memory in the host system.
  2. Program the base address with the write_map_table with the physical address of the table.
  3. Set the write address register with the offset in block where Traffic generator needs to write the data.
  4. Set how many number of bursts BAS should write in host memory in the WRITE_COUNT register.
  5. Set the enable bit to start traffic generation.

Did you find the information on this page useful?

Characters remaining:

Feedback Message