Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide
ID
683517
Date
2/06/2022
Public
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3.5.2.6.1. Build and Install Netdev Driver
3.5.2.6.2. Enable VFs if SRIOV is Supported
3.5.2.6.3. Configure the Number of Channels Supported on the Device
3.5.2.6.4. Configure the MTU Value
3.5.2.6.5. Configure the Device Communication
3.5.2.6.6. Configure Transmit Queue Selection Mechanism
3.5.2.6.7. Test Procedure by Using Name Space Environment
3.5.2.6.8. PIO Test
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If the BAS support is enabled on hardware, enable the following flag in: user/common/include/ifc_libmqdma.h
#define PCIe_SLOT 0 /* 0 – x16, 1 – x8 */
Commands:
- To verify the write operation:
./cli/perfq_app/ perfq_app -b\ 0000:01:00.0 -s 512 -e -t
Figure 49. BAS Write Operation - To verify the read operation:
./cli/perfq_app/perfq_app -b\ 0000:01:00.0 -s 512 -e -r
Figure 50. BAS Read Operation - To verify the write and read operation:
./cli/perfq_app/perfq_app -b\ 0000:01:00.0 -s 512 -e -z
Figure 51. BAS Write and Read OperationPerformance test:
The below log is collected on Gen3x16 H-tile./cli/perfq_app/perfq_app -b\ 0000:01:00.0 -s 1048576 –bas-perf
Figure 52. Performance Test