V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Document Table of Contents

1.9. Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses no core device resources (no ALMs and no embedded memory).

The Avalon-MM with DMA V-Series variants include an Avalon-MM DMA bridge implemented in soft logic that operates as a front end to the hardened protocol stack. The following table shows the typical expected device resource utilization for selected configurations using the current version of the Quartus® Prime software targeting an V-Series device. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 50.

Table 7.  Resource Utilization V-Series Avalon-MM DMA for PCI Express

Data Rate, Number of Lanes, and Interface Width


M20K Memory Blocks

Logic Registers

Gen2 x4 128 4300 29 5800

Gen2 x8 128




Gen3 x8 256




Note: Soft calibration of the transceiver module requires additional logic. The amount of logic required depends upon the configuration.

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