New features in the Quartus® Prime 16.1 software release:
- Increased maximum DMA transfer size for the 128- and 256-bit interfaces to 1 megabyte (MB).
The V-Series Avalon-MM DMA for PCI Express supports the following features:
- Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
- Native support for Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x2, Gen3 x4, Gen3 x8 for Endpoints. The variant downtrains when plugged into a lesser link width or changes to a different maximum link rate.
- Dedicated 16 kilobyte (KB) receive buffer.
- Optional hard reset controller for Gen2.
- Support for 128- or 256-bit Avalon-MM interface to Application Layer with embedded DMA up to Gen3 ×8 data rate.
- Support for 32- or 64-bit addressing for the Avalon-MM interface to the Application Layer.
- Platform Designer design example demonstrating parameterization, design modules, and connectivity.
- Extended credit allocation settings to better optimize the RX buffer space based on application type.
- Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.
- Support for Configuration Space Bypass Mode (in Arria® V GZ and Stratix® V), allowing you to design a custom Configuration Space and support multiple functions.
- Support for Gen3 PIPE simulation.
- Easy to use:
- Flexible configuration.
- No license requirement.
- Design examples to get started.
|Feature||128-Bit Interface||256-Bit Interface|
|Root Port||Not supported||Supported|
|Tags supported||16||16 or 256|
|Maximum descriptor size||1 MB||1 MB|
|Maximum payload size||128 or 256||128 or 256|
|Immediate write1||Not supported||Supported|
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