V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

4.5.1. CvP Registers

Table 31.  CvP Status The CvP Status register allows software to monitor the CvP status signals.
Bits Register Description Reset Value Access
[31:26] Reserved 0x00 RO
[25] PLD_CORE_READY. From FPGA fabric. This status bit is provided for debug. Variable RO
[24] PLD_CLK_IN_USE. From clock switch module to fabric. This status bit is provided for debug. Variable RO
[23] CVP_CONFIG_DONE. Indicates that the FPGA control block has completed the device configuration via CvP and there were no errors. Variable RO
[22] Reserved Variable RO
[21] USERMODE. Indicates if the configurable FPGA fabric is in user mode. Variable RO
[20] CVP_EN. Indicates if the FPGA control block has enabled CvP mode. Variable RO
[19] CVP_CONFIG_ERROR. Reflects the value of this signal from the FPGA control block, checked by software to determine if there was an error during configuration. Variable RO
[18] CVP_CONFIG_READY. Reflects the value of this signal from the FPGA control block, checked by software during programming algorithm. Variable RO
[17:0] Reserved Variable RO
Table 32.  CvP Mode Control The CvP Mode Control register provides global control of the CvP operation.

Bits

Register Description

Reset Value

Access

[31:16]

Reserved.

0x0000

RO

[15:8]

CVP_NUMCLKS.

This is the number of clocks to send for every CvP data write. Set this field to one of the values below depending on your configuration image:

  • 0x01 for uncompressed and unencrypted images
  • 0x04 for uncompressed and encrypted images
  • 0x08 for all compressed images

0x00

RW

[7:3]

Reserved.

0x0

RO

[2]

CVP_FULLCONFIG. Request that the FPGA control block reconfigure the entire FPGA including the V-Series Hard IP for PCI Express, bring the PCIe link down.

1’b0

RW

[1]

HIP_CLK_SEL. Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The following encodings are defined:

  • 1: Selects internal clock from PMA which is required for CVP_MODE.
  • 0: Selects the clock from soft logic fabric. This setting should only be used when the fabric is configured in USER_MODE with a configuration file that connects the correct clock.

To ensure that there is no clock switching during CvP, you should only change this value when the Hard IP for PCI Express has been idle for 10 µs and wait 10 µs after changing this value before resuming activity.

1’b0

RW

[0]

CVP_MODE. Controls whether the IP core is in CVP_MODE or normal mode. The following encodings are defined:

  • 1:CVP_MODE is active. Signals to the FPGA control block active and all TLPs are routed to the Configuration Space. This CVP_MODE cannot be enabled if CVP_EN = 0.
  • 0: The IP core is in normal mode and TLPs are routed to the FPGA fabric.

1’b0

RW

Table 33.  CvP Data Registers

The following table defines the CvP Data registers. For 64-bit data, the optional CvP Data2 stores the upper 32 bits of data. Programming software should write the configuration data to these registers. If you Every write to these register sets the data output to the FPGA control block and generates <n> clock cycles to the FPGA control block as specified by the CVP_NUM_CLKS field in the CvP Mode Control register. Software must ensure that all bytes in the memory write dword are enabled. You can access this register using configuration writes, alternatively, when in CvP mode, these registers can also be written by a memory write to any address defined by a memory space BAR for this device. Using memory writes should allow for higher throughput than configuration writes.

Bits

Register Description

Reset Value

Access

[31:0]

Upper 32 bits of configuration data to be transferred to the FPGA control block to configure the device. You can choose 32- or 64-bit data.

0x00000000

RW

[31:0]

Lower 32 bits of configuration data to be transferred to the FPGA control block to configure the device.

0x00000000

RW

Table 34.  CvP Programming Control Register This register is written by the programming software to control CvP programming.

Bits

Register Description

Reset Value

Access

[31:2]

Reserved.

0x0000

RO

[1]

START_XFER. Sets the CvP output to the FPGA control block indicating the start of a transfer.

1’b0

RW

[0]

CVP_CONFIG. When asserted, instructs that the FPGA control block begin a transfer via CvP.

1’b0

RW

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