V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

3.2. Base Address Register (BAR) Settings

The type and size of BARs available depend on port type.

Table 17.  BAR Registers

Parameter

Value

Description

Type

Disabled

64-bit prefetchable memory

32-bit non-prefetchable memory

32-bit prefetchable memory

I/O address space

If you select 64-bit prefetchable memory, 2 contiguous BARs are combined to form a 64-bit prefetchable BAR; you must set the higher numbered BAR to Disabled. A non-prefetchable 64‑bit BAR is not supported because in a typical system, the Root Port Type 1 Configuration Space sets the maximum non‑prefetchable memory window to 32 bits. The BARs can also be configured as separate 32‑bit memories.

Defining memory as prefetchable allows contiguous data to be fetched ahead. Prefetching memory is advantageous when the requestor may require more data from the same region than was originally requested. If you specify that a memory is prefetchable, it must have the following 2 attributes:

  • Reads do not have side effects such as changing the value of the data read
  • Write merging is allowed

Size

N/A Platform Designer automatically calculates the required size after you connect your components.

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