V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP

If your design meets the following criteria:

  • It enables CvP
  • It includes an additional transceiver PHY that connect to the same Transceiver Reconfiguration Controller

then you must connect the PCIe refclk signal to the mgmt_clk_clk signal of the Transceiver Reconfiguration Controller and the additional transceiver PHY. In addition, if your design includes more than one Transceiver Reconfiguration Controller on the same side of the FPGA, they all must share the mgmt_clk_clk signal.

For more information about using the Transceiver Reconfiguration Controller, refer to the Transceiver Reconfiguration Controller chapter in the Altera Transceiver PHY IP Core User Guide.

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