V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

1.10. V-Series Recommended Speed Grades

Altera recommends setting the Quartus® Prime Analysis & Synthesis Settings Optimization Technique to Speed when the Application Layer clock frequency is 250 MHz. For information about optimizing synthesis, refer to Setting Up and Running Analysis and Synthesis in Quartus® Prime Help. For more information about how to effect the Optimization Technique settings, refer to Area and Timing Optimization in volume 2 of the Quartus® Prime Handbook.

Table 8.  Arria V Recommended Speed Grades for All Link Widths, Link Widths, and Application Layer Clock Frequencies

Link Rate

Link Width

Interface Width

Application Clock Frequency (MHz)

Recommended Speed Grades

Gen1

×1

64 bits

62.5 3,125

–4,–5,–6

×2

64 bits

125

–4,–5,–6

×4

64 bits

125

–4,–5,–6

×8

128 bits

125

–4,–5,–6

Gen2

×1

64 bits

125

–4,–5

×2

64 bits

125

–4,–5

×4

128 bits

125

–4,–5

Table 9.  Arria V GZ Recommended Speed Grades for All Widths, Link Widths, and Application Layer Clock Frequencies

Link Rate

Link Width

Interface Width

Application Clock Frequency (MHz)

Recommended Speed Grades

Gen1

x1

64 bits

62.5 4,125

–1, –2, –3, –4

x2

64 bits

125

–1, –2, –3, –4

x4

64 bits

125

–1, –2, –3, –4

x8

64 bits

250

–1, –2, –3 5

x8

128 Bits

125

–1, –2, –3, –4

Gen2

x1

64 bits

125

–1, –2, –3, –4

x2

64 bits

125

–1, –2, –3, –4

x4

64 bits

250

–1, –2, –3 (5)

x4

128 bits

125

–1, –2, –3, –4

x8

128 bits

250

–1, –2, –3 (5)

x8

256 bits

125

–1, –2, –3, –4

Gen3

x1

64 bits

125

–1, –2, –3, –4

x2

64 bits

250

–1, –2, –3, –4

x2

128 bits

125

–1, –2, –3, –4

x4

128 bits

250

–1, –2, –3(5)

x4

256 bits

125

–1, –2, –3,–4

x8

256 bits

250

–1, –2, –3(5)

Table 10.  Cyclone V Recommended Speed Grades for All Link Widths, Link Widths, and Application Layer Clock Frequencies The Gen2 data rate requires Cyclone V GT devices.

Link Rate

Link Width

Interface Width

Application Clock Frequency (MHz)

Recommended Speed Grades

Gen1

×1

64 bits

62.5 6,125

–6, –7,–8

×2

64 bits

125

–6, –7,–8

×4

64 bits

125

–6, –7,–8

Gen2

×1

64 bits

125

–7

×2

64 bits

125

–7

×4

128 bits

125

–7

Table 11.  Stratix V Recommended Speed Grades for All Widths, Link Widths, and Application Layer Clock Frequencies

Link Rate

Link Width

Interface Width

Application Clock Frequency (MHz)

Recommended Speed Grades

Gen1

x1

64 bits

62.5 7,125

–1, –2, –3, –4

x2

64 bits

125

–1, –2, –3, –4

x4

64 bits

125

–1, –2, –3, –4

x8

64 bits

250

–1, –2, –3 5 8

x8

128 Bits

125

–1, –2, –3, –4

Gen2

x1

64 bits

125

–1, –2, –3, –4

x2

64 bits

125

–1, –2, –3, –4

x4

64 bits

250

–1, –2, –3 5

x4

128 bits

125

–1, –2, –3, –4

x8

128 bits

250

–1, –2, –3 5

x8

256 bits

125

–1, –2, –3, –4

Gen3

x1

64 bits

125

–1, –2, –3, –4

x2

64 bits

250

–1, –2, –3, –4

x2

128 bits

125

–1, –2, –3, –4

x4

128 bits

250

–1, –2, –3 5

x4

256 bits

125

–1, –2, –3,–4

x8

256 bits

250

–1, –2, –3 5

3 This is a power-saving mode of operation
4 This is a power-saving mode of operation
5 The -4 speed grade is also possible for this configuration; however, it requires significant effort by the end user to close timing.
6 This is a power-saving mode of operation
7 This is a power-saving mode of operation
8 The -4 speed grade is also possible for this configuration; however, it requires significant effort by the end user to close timing.

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