V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

4.6.2. Uncorrectable Internal Error Status Register

Table 36.  Uncorrectable Internal Error Status Register This register reports the status of the internally checked errors that are uncorrectable. When specific errors are enabled by the Uncorrectable Internal Error Mask register, they are handled as Uncorrectable Internal Errors as defined in the PCI Express Base Specification 3.0. This register is for debug only. It should only be used to observe behavior, not to drive custom logic. The access code RW1CS represents Read Write 1 to Clear Sticky.

Bits

Register Description

Reset Value

Access

[31:12]

Reserved.

0

RO

[11]

When set, indicates an RX buffer overflow condition in a posted request or Completion

0

RW1CS

[10]

Reserved.

0

RO

[9]

When set, indicates a parity error was detected on the Configuration Space to TX bus interface

0

RW1CS

[8]

When set, indicates a parity error was detected on the TX to Configuration Space bus interface

0

RW1CS

[7]

When set, indicates a parity error was detected in a TX TLP and the TLP is not sent.

0

RW1CS

[6]

When set, indicates that the Application Layer has detected an uncorrectable internal error.

0

RW1CS

[5]

When set, indicates a configuration error has been detected in CvP mode which is reported as uncorrectable. This bit is set whenever a CVP_CONFIG_ERROR rises while in CVP_MODE.

0

RW1CS

[4]

When set, indicates a parity error was detected by the TX Data Link Layer.

0

RW1CS

[3]

When set, indicates a parity error has been detected on the RX to Configuration Space bus interface.

0

RW1CS

[2]

When set, indicates a parity error was detected at input to the RX Buffer.

0

RW1CS

[1]

When set, indicates a retry buffer uncorrectable ECC error.

0

RW1CS

[0]

When set, indicates a RX buffer uncorrectable ECC error.

0

RW1CS

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