V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

5. Error Handling

Each PCI Express compliant device must implement a basic level of error management and can optionally implement advanced error management. The IP core implements both basic and advanced error reporting. Error handling for a Root Port is more complex than that of an Endpoint.

Table 42.  Error ClassificationThe PCI Express Base Specification defines three types of errors, outlined in the following table.

Type

Responsible Agent

Description

Correctable

Hardware

While correctable errors may affect system performance, data integrity is maintained.

Uncorrectable, non-fatal

Device software

Uncorrectable, non-fatal errors are defined as errors in which data is lost, but system integrity is maintained. For example, the fabric may lose a particular TLP, but it still works without problems.

Uncorrectable, fatal

System software

Errors generated by a loss of data and system failure are considered uncorrectable and fatal. Software must determine how to handle such errors: whether to reset the link or implement other means to minimize the problem.

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