V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

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ID 683514
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM DMA 3. Parameter Settings 4. Registers 5. Error Handling 6. PCI Express Protocol Stack 7. V-Series Avalon-MM DMA for PCI Express 8. Transceiver PHY IP Reconfiguration A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe B. V-Series Interface for PCIe Solutions User Guide Archive C. Document Revision History
1. Datasheet x
1.1. V-Series Avalon-MM DMA Interface for PCIe* Datasheet 1.2. Features 1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces for V-Series Devices 1.4. Release Information 1.5. V-Series Device Family Support 1.6. Design Examples 1.7. Debug Features 1.8. IP Core Verification 1.9. Resource Utilization 1.10. V-Series Recommended Speed Grades 1.11. Creating a Design for PCI Express
1.8. IP Core Verification x
1.8.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM DMA x
2.1. Understanding the Avalon-MM DMA Ports 2.2. Generating the Testbench 2.3. Simulating the Example Design in ModelSim* 2.4. Running a Gate-Level Simulation 2.5. Generating Synthesis Files 2.6. Compiling the Design 2.7. Creating a Quartus® Prime Project
2.2. Generating the Testbench x
2.2.1. Understanding the Simulation Generated Files 2.2.2. Understanding Simulation Log File Generation
3. Parameter Settings x
3.1. System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. PCI Express and PCI Capabilities Parameters 3.5. PCIe Address Space Settings
3.4. PCI Express and PCI Capabilities Parameters x
3.4.1. Device Capabilities 3.4.2. Error Reporting 3.4.3. Link Capabilities 3.4.4. MSI and MSI-X Capabilities 3.4.5. Power Management
4. Registers x
4.1. Correspondence between Configuration Space Registers and the PCIe Specification 4.2. Type 0 Configuration Space Registers 4.3. Type 1 Configuration Space Registers 4.4. PCI Express Capability Structures 4.5. Intel-Defined VSEC Registers 4.6. Advanced Error Reporting Capability 4.7. DMA Descriptor Controller Registers 4.8. Control Register Access (CRA) Avalon-MM Slave Port
4.5. Intel-Defined VSEC Registers x
4.5.1. CvP Registers
4.6. Advanced Error Reporting Capability x
4.6.1. Uncorrectable Internal Error Mask Register 4.6.2. Uncorrectable Internal Error Status Register 4.6.3. Correctable Internal Error Mask Register 4.6.4. Correctable Internal Error Status Register
4.7. DMA Descriptor Controller Registers x
4.7.1. Read DMA Descriptor Controller Registers 4.7.2. Write DMA Descriptor Controller Registers 4.7.3. Read DMA and Write DMA Descriptor Format 4.7.4. Read DMA Example 4.7.5. Software Program for Simultaneous Read and Write DMA
5. Error Handling x
5.1. Physical Layer Errors 5.2. Data Link Layer Errors 5.3. Transaction Layer Errors 5.4. Error Reporting and Data Poisoning 5.5. Uncorrectable and Correctable Error Status Bits
6. PCI Express Protocol Stack x
6.1. Top-Level Interfaces 6.2. Data Link Layer 6.3. Physical Layer
6.1. Top-Level Interfaces x
6.1.1. Avalon-MM DMA Interface 6.1.2. Clocks and Reset 6.1.3. Transceiver Reconfiguration 6.1.4. Interrupts 6.1.5. PIPE
7. V-Series Avalon-MM DMA for PCI Express x
7.1. Understanding the Internal DMA Descriptor Controller 7.2. Understanding the External DMA Descriptor Controller
8. Transceiver PHY IP Reconfiguration x
8.1. Connecting the Transceiver Reconfiguration Controller IP Core 8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
C. Document Revision History x
C.1. Document Revision History for the V-Series Avalon® Memory Mapped (Avalon-MM) DMA Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Registers
5. Error Handling
6. PCI Express Protocol Stack
7. V-Series Avalon-MM DMA for PCI Express
8. Transceiver PHY IP Reconfiguration
A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe
B. V-Series Interface for PCIe Solutions User Guide Archive
C. Document Revision History

4.7.3. Read DMA and Write DMA Descriptor Format

Read and write descriptors are stored in separate descriptor tables in PCIe* system memory. Each table can store up to 128 descriptors. Each descriptor is 8 DWORDs, or 32 bytes. The Read DMA and Write DMA descriptor tables start at a 0x200 byte offset from the addresses programmed into the Read Status and Descriptor Base and Write Status and Descriptor Base address registers.

Programming RD_DMA_LAST_PTR or WR_DMA_LAST_PTR registers triggers the Read or Write Descriptor Controller descriptor table fetch process. Consequently, writing these registers must be the last step in setting up DMA transfers.

Note: Because the DMA Descriptor Controller uses FIFOs to store descriptor table entries, you cannot reprogram the DMA Descriptor Controller once it begins the transfers specified in the descriptor table.
Table 39.  Read Descriptor FormatYou must also use this format for the Read and Write Data Movers on their Avalon® -ST when you use your own DMA Controller.

Address Offset

Register Name

Description

0x00

RD_LOW_SRC_ADDR

Lower DWORD of the read DMA source address. Specifies the address in PCIe* system memory from which the Read Data Mover fetches data.

0x04

RD_HIGH_SRC_ADDR

Upper DWORD of the read DMA source address. Specifies the address in PCIe* system memory from which the Read Data Mover fetches data.

0x08

RD_CTRL_LOW_DEST_ADDR

Lower DWORD of the read DMA destination address. Specifies the address in the Avalon-MM domain to which the Read Data Mover writes data.

0x0C

RD_CTRL_HIGH_DEST_ADDR

Upper DWORD of the read DMA destination address. Specifies the address in the Avalon-MM domain to which the Read Data Mover writes data.

0x10 CONTROL Specifies the following information:
  • [31:25] Reserved must be 0.
  • [24:18] ID. Specifies the Descriptor ID. Descriptor ID 0 is at the beginning of the table. For descriptor tables of the maximum size, Descriptor ID 127 is at the end of the table.
  • [17:0] SIZE. The transfer size in DWORDs. Must be non-zero. The maximum transfer size is (1 MB - 4 bytes). If the specified transfer size is less than the maximum, the transfer size is the actual size entered.
0x14 - 0x1C Reserved N/A
Table 40.  Write Descriptor Format

Address Offset

Register Name

Description

0x00

WR_LOW_SRC_ADDR

Lower DWORD of the write DMA source address. Specifies the address in the Avalon® MM domain from which the Write Data Mover fetches data.

0x04

WR_HIGH_SRC_ADDR

Upper DWORD of the write DMA source address. Specifies the address in the Avalon® MM domain from which the Write Data Mover fetches data.

0x08

WR_CTRL_LOW_DEST_ADDR

Lower DWORD of the Write Data Mover destination address. Specifies the address in PCIe* system memory to which the Write DMA writes data.

0x0C

WR_CTRL_HIGH_DEST_ADDR

Upper DWORD of the write DMA destination address. Specifies the address in PCIe* system memory to which the Write Data Mover writes data.

0x10 CONTROL Specifies the following information:
  • [31:25]: Reserved must be 0.
  • [24:18]:ID: Specifies the Descriptor ID. Descriptor ID 0 is at the beginning of the table. Descriptor ID is at the end of the table.
  • [17:0] :SIZE: The transfer size in DWORDs. Must be non-zero. The maximum transfer size is (1 MB - 4 bytes). If the specified transfer size is less than the maximum, the transfer size is the actual size entered.
0x14 - 0x1C Reserved N/A
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