V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

2.2.1. Understanding the Simulation Generated Files

Table 14.   Platform Designer Generation Output Files  

Directory

Description

<testbench_dir>/<variant_name>/testbench

Includes testbench subdirectories for the Aldec, Cadence, Mentor, and Synopsys simulation tools with the required libraries and simulation scripts.

<testbench_dir>/<variant_name>/testbench/<cad_vendor>

Includes the HDL source files and scripts for the simulation testbench.

<testbench_dir>/<variant_name>/testbench/<variant_namer>_tb Includes HDL design files

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