V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Document Table of Contents

2.2.1. Understanding the Simulation Generated Files

Table 14.   Platform Designer Generation Output Files  




Includes testbench subdirectories for the Aldec, Cadence, Mentor, and Synopsys simulation tools with the required libraries and simulation scripts.


Includes the HDL source files and scripts for the simulation testbench.

<testbench_dir>/<variant_name>/testbench/<variant_namer>_tb Includes HDL design files