V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

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ID 683514
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM DMA 3. Parameter Settings 4. Registers 5. Error Handling 6. PCI Express Protocol Stack 7. V-Series Avalon-MM DMA for PCI Express 8. Transceiver PHY IP Reconfiguration A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe B. V-Series Interface for PCIe Solutions User Guide Archive C. Document Revision History
1. Datasheet x
1.1. V-Series Avalon-MM DMA Interface for PCIe* Datasheet 1.2. Features 1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces for V-Series Devices 1.4. Release Information 1.5. V-Series Device Family Support 1.6. Design Examples 1.7. Debug Features 1.8. IP Core Verification 1.9. Resource Utilization 1.10. V-Series Recommended Speed Grades 1.11. Creating a Design for PCI Express
1.8. IP Core Verification x
1.8.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM DMA x
2.1. Understanding the Avalon-MM DMA Ports 2.2. Generating the Testbench 2.3. Simulating the Example Design in ModelSim* 2.4. Running a Gate-Level Simulation 2.5. Generating Synthesis Files 2.6. Compiling the Design 2.7. Creating a Quartus® Prime Project
2.2. Generating the Testbench x
2.2.1. Understanding the Simulation Generated Files 2.2.2. Understanding Simulation Log File Generation
3. Parameter Settings x
3.1. System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. PCI Express and PCI Capabilities Parameters 3.5. PCIe Address Space Settings
3.4. PCI Express and PCI Capabilities Parameters x
3.4.1. Device Capabilities 3.4.2. Error Reporting 3.4.3. Link Capabilities 3.4.4. MSI and MSI-X Capabilities 3.4.5. Power Management
4. Registers x
4.1. Correspondence between Configuration Space Registers and the PCIe Specification 4.2. Type 0 Configuration Space Registers 4.3. Type 1 Configuration Space Registers 4.4. PCI Express Capability Structures 4.5. Intel-Defined VSEC Registers 4.6. Advanced Error Reporting Capability 4.7. DMA Descriptor Controller Registers 4.8. Control Register Access (CRA) Avalon-MM Slave Port
4.5. Intel-Defined VSEC Registers x
4.5.1. CvP Registers
4.6. Advanced Error Reporting Capability x
4.6.1. Uncorrectable Internal Error Mask Register 4.6.2. Uncorrectable Internal Error Status Register 4.6.3. Correctable Internal Error Mask Register 4.6.4. Correctable Internal Error Status Register
4.7. DMA Descriptor Controller Registers x
4.7.1. Read DMA Descriptor Controller Registers 4.7.2. Write DMA Descriptor Controller Registers 4.7.3. Read DMA and Write DMA Descriptor Format 4.7.4. Read DMA Example 4.7.5. Software Program for Simultaneous Read and Write DMA
5. Error Handling x
5.1. Physical Layer Errors 5.2. Data Link Layer Errors 5.3. Transaction Layer Errors 5.4. Error Reporting and Data Poisoning 5.5. Uncorrectable and Correctable Error Status Bits
6. PCI Express Protocol Stack x
6.1. Top-Level Interfaces 6.2. Data Link Layer 6.3. Physical Layer
6.1. Top-Level Interfaces x
6.1.1. Avalon-MM DMA Interface 6.1.2. Clocks and Reset 6.1.3. Transceiver Reconfiguration 6.1.4. Interrupts 6.1.5. PIPE
7. V-Series Avalon-MM DMA for PCI Express x
7.1. Understanding the Internal DMA Descriptor Controller 7.2. Understanding the External DMA Descriptor Controller
8. Transceiver PHY IP Reconfiguration x
8.1. Connecting the Transceiver Reconfiguration Controller IP Core 8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
C. Document Revision History x
C.1. Document Revision History for the V-Series Avalon® Memory Mapped (Avalon-MM) DMA Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Registers
5. Error Handling
6. PCI Express Protocol Stack
7. V-Series Avalon-MM DMA for PCI Express
8. Transceiver PHY IP Reconfiguration
A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe
B. V-Series Interface for PCIe Solutions User Guide Archive
C. Document Revision History

C.1. Document Revision History for the V-Series Avalon® Memory Mapped (Avalon-MM) DMA Interface for PCIe* Solutions User Guide

Date

Version

Changes Made

2021.06.03 18.0.1 Mentioned in the Features section that this IP supports the Separate Reference Clock No Spread Spectrum (SRNS) architecture and not the Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture.
2019.12.23 18.0.1 Changed the name of the 1A state of the ltssmstate signals to Recovery.Speed to follow the PCIe Specifications.
2019.05.23 18.0.1 Added a note clarifying that the 24-bit Class Code register is divided into three 8-bit fields: Base Class Code, Sub-Class Code and Programming Interface.
2019.04.30 18.0.1 Updated Table 3 to show that the Avalon-MM DMA feature is not supported in Root Port mode.
2018.08.28 18.0.1 Added the step to invoke vsim to the instructions for simulating the example design in ModelSim.
2018.06.15 18.0.1

Added note that Flush reads are not supported when burst mode for BAR2 is enabled.

Updated the list of configurations supported by the Avalon-MM and Avalon-MM with DMA variants.

2018.05.07 18.0

Changed all references to Intel® Cyclone® 10 to Intel® Cyclone® 10 GX.

2017.10.06 17.1 Made the following change to the user guide:
  • Added support for Intel® Cyclone® 10 GX devices.
  • Added optional parameter to invert the RX polarity.
  • Corrected Feature Comparison for all Hard IP for PCI Express IP Core table: The Avalon-MM DMA interface does not automatically handle out-of-order completions.
  • Added missing sequence of programming steps in DMA Descriptor Controller Registers.
  • Rebranded as Intel.
  • Corrected minor errors and typos.
2017.05.26 17.0 Made the following changes to the user guide:
  • Added note that starting with the Intel® Quartus® Prime Pro Edition Software, version 17.0, the QSF assignments in the following answer What assignments do I need for a PCIe Gen1, Gen2 or Gen3 design that targets an Intel® Arria® 10 ES2, ES3 or production device? are already included in the design.
2017.05.08 17.0 Made the following changes to the user guide:
  • Corrected Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces table. Out-of-order Completions are not supported transparently for the Avalon-MM with DMA interface.
2017.03.15 16.1.1 Made the following changes:
  • Rebranded as Intel.
2016.10.28 16.1 Made the following to the IP core changes:
  • Increased the max DMA transfer to 1 MB for both the 128- and 256-bit interfaces.

Made the following changes to the user guide:

  • Corrected the number of tags supported in the Feature Comparison for all Hard IP for PCI Express IP Cores table.
  • Added PCIe bifurcation to the Feature Comparison for all Hard IP for PCI Express IP Cores table. PCI bifurcation is not supported.
  • Removed reference to a Linux software driver for the DMA modules which is not available.
  • Added section covering design example limitations.
2016.05.02 16.0 Made the following changes:
  • Redesigned the 128-bit interface to the Application Layer resulting in consistently high throughput for both on-chip and external memory.
  • Added simulation support for Gen3 PIPE mode using the ModelSim, VCS, and NCSim simulators.
  • Revised discussion of the DMA Descriptor Controller in the Avalon-MM with DMA IP Core Architecture.
  • Revised Read DMA Example to reflect current maximum transfer size of 64 KB for 256-bit interface. The example now corresponds to an example design provided in the <install_dir>.
  • Corrected description of Write Descriptor Table Avalon-MM Slave Port.
2015.11.30 15.1
  • Added description of the Altera PCIe Reconfig Driver in the Connecting the Transceiver Reconfiguration Controller IP Core topic.
  • Added note explaining that the Getting Started design examples do not generate all the files necessary to download to an Altera FPGA Development Kit. Provided link to AN 690: PCI Express DMA Reference Design for Stratix V Devices and AN 708: PCI Express DMA Reference Design Using External DDR3 Memory for Stratix V and Arria V GZ Devices that includes all necessary files.
  • Added a FAQ chapter.
  • Removed dlup signal. This signal is no longer part of the Hard IP Status interface.
  • Fixed minor errors and typos.
2014.12.18 14.1 Made the following changes:
  • Updated the instructions to create a Quartus II project and compile the design in the Getting Started with the Avalon-MM DMA chapter.
  • Added links to the PCI Express Multi-Channel DMA Interface Example Design User Guide and the Avalon-MM DMA FIFO Example Design User Guide.
2014.12.15 14.1 Made the following changes to the Intel® Arria® 10 user guide:

  • In the Getting Started chapter, corrected directory path for the simulation.

  • Added the fact that the RX Burst Master only support dword granularity.
  • Added definitions for test_in[2], test_in[6] and test_in[7].
  • Added instructions for Quartus II compilation.
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