V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

8. Transceiver PHY IP Reconfiguration

As silicon progresses towards smaller process nodes, circuit performance is affected by variations due to process, voltage, and temperature (PVT). Consequently, Gen3 designs require offset cancellation and adaptive equalization (AEQ) to ensure correct operation. Intel’s Platform Designer example designs all include Transceiver Reconfiguration Controller and Intel PCIe Reconfig Driver IP cores that automatically perform these functions during the LTSSM equalization states.

As silicon progresses towards smaller process nodes, circuit performance is affected by variations due to process, voltage, and temperature (PVT). Designs typically require offset cancellation to ensure correct operation. At Gen2 data rates, designs also require DCD calibration. Intel’s Platform Designer example designs all include Transceiver Reconfiguration Controller and Intel PCIe Reconfig Driver IP cores to perform these functions.

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