V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

4.6.3. Correctable Internal Error Mask Register

Table 37.  Correctable Internal Error Mask RegisterThe Correctable Internal Error Mask register controls which errors are forwarded as Internal Correctable Errors. This register is for debug only.

Bits

Register Description

Reset Value

Access

[31:8]

Reserved.

0

RO

[7] Reserved. 1 RO

[6]

Mask for Corrected Internal Error reported by the Application Layer.

1

RWS

[5]

Mask for configuration error detected in CvP mode.

1

RWS

[4:2]

Reserved.

0

RO

[1]

Mask for retry buffer correctable ECC error.

1

RWS

[0]

Mask for RX Buffer correctable ECC error.

1

RWS

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