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1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Registers
5. Error Handling
6. PCI Express Protocol Stack
7. V-Series Avalon-MM DMA for PCI Express
8. Transceiver PHY IP Reconfiguration
A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe
B. V-Series Interface for PCIe Solutions User Guide Archive
C. Document Revision History
1.1. V-Series Avalon-MM DMA Interface for PCIe* Datasheet
1.2. Features
1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces for V-Series Devices
1.4. Release Information
1.5. V-Series Device Family Support
1.6. Design Examples
1.7. Debug Features
1.8. IP Core Verification
1.9. Resource Utilization
1.10. V-Series Recommended Speed Grades
1.11. Creating a Design for PCI Express
4.1. Correspondence between Configuration Space Registers and the PCIe Specification
4.2. Type 0 Configuration Space Registers
4.3. Type 1 Configuration Space Registers
4.4. PCI Express Capability Structures
4.5. Intel-Defined VSEC Registers
4.6. Advanced Error Reporting Capability
4.7. DMA Descriptor Controller Registers
4.8. Control Register Access (CRA) Avalon-MM Slave Port
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This section describes the top-level interfaces in the PCIe variant when it includes the high-performance, burst-capable read data mover and write data mover modules.
Depending on the device, the interface to the Application Layer can be 128 or 256 bits.
Avalon-MM DMA Bridge with Internal Descriptor Controller
Avalon-MM DMA Bridge with Internal Descriptor Controller
Avalon-MM DMA Bridge with External Descriptor Controller
This section describes the interfaces that are required to implement the DMA. All other interfaces are described in the next section, Avalon-MM Interface to the Application Layer.
Section Content
Avalon-MM DMA Interfaces when Descriptor Controller Is Internally Instantiated
Read Data Mover
Write DMA Avalon-MM Master Port
RX Master Module
Non-Bursing Slave Module
32-Bit Control Register Access (CRA) Slave Signals
Avalon-ST Descriptor Control Interface when Instantiated Separately
Descriptor Controller Interfaces when Instantiated Internally