Intel® Quartus® Prime Standard Edition User Guide: Getting Started

ID 683475
Date 12/16/2019
Document Table of Contents

2.11. Managing Projects Revision History

Document Version Intel® Quartus® Prime Version Changes
2018.09.24 18.1.0
  • Subdivided "Exporting, Archiving, and Migrating Projects" into separate sections.
  • Added "Specifying the Target Device or Board" topic.
  • Divided "Introduction to Intel FPGA IP Cores" into separate chapter.
  • Moved "IP Core Best Practices" topic to Introduction to Intel FPGA IP Cores chapter.
  • Moved "Factors Affecting Compilation Results" topic to Design Compilation: Intel Quartus Prime Standard Edition User Guide.
2018.02.11 18.0.0
  • Added description of | as root partition hierarchy path in Design Partitions Window.
  • Removed "Scripting IP Simulation" and "Generating a Combined Simulation Script" topics. These features are supported only for Intel® Arria® 10 devices in Intel® Quartus® Prime Standard Edition.
  • Added link to "Scripting IP Simulation" in the Introduction to Intel® FPGA IP Cores.
Date Version Changes
2017.11.06 17.1.0
  • Revised product branding for Intel® standards.
  • Changed instances of Qsys to Platform Designer (Standard)
  • Revised topics on Intel® FPGA IP Evaluation Mode (formerly OpenCore).
  • Removed -compatible attribute from export_design command content.
  • Updated IP Core Upgrade Status table with new icons, and added row for IP Component Outdated status.
2017.05.08 17.0.0
  • Added topic on Back-Annotate Assignments command.
2016.10.31 16.1.0
  • Updated screenshots.
2016.05.03 16.0.0 Removed statements about serial equivalence when using multiple processors.
2016.02.09 15.1.1
  • Clarified instructions for Generating a Combined Simulator Setup Script.
  • Clarified location of Save project output files in specified directory option.
2015.11.02 15.1.0 Changed instances of Quartus II to Intel® Quartus® Prime .
2015.05.04 15.0.0
  • Added description of design templates feature.
  • Updated screenshot for DSE II GUI.
  • Added qsys_script IP core instantiation information.
  • Described changes to generating and processing of instance and entity names.
  • Added description of upgrading IP cores at the command line.
  • Updated procedures for upgrading and migrating IP cores.
  • Gate level timing simulation supported only for Cyclone IV and Stratix IV devices.
2014.12.15 14.1.0
  • Updated content for DSE II GUI and optimizations.
  • Added information about new Assignments > Settings > IP Settings that control frequency of synthesis file regeneration and automatic addition of IP files to the project.


  • Added information about specifying parameters for IP cores targeting Arria 10 devices.
  • Added information about the latest IP output for version 14.0a10 targeting Arria 10 devices.
  • Added information about individual migration of IP cores to the latest devices.
  • Added information about editing existing IP variations.
2014.06.30 14.0.0
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
November 2013 13.1.0
  • Conversion to DITA format
May 2013 13.0.0
  • Overhaul for improved usability and updated information.
June 2012 12.0.0
  • Removed survey link.
  • Updated information about VERILOG_INCLUDE_FILE.
November 2011 10.1.1 Template update.
December 2010 10.1.0
  • Changed to new document template.
  • Removed Figure 4–1, Figure 4–6, Table 4–2.
  • Moved “Hiding Messages” to Help.
  • Removed references about the set_user_option command.
  • Removed Classic Timing Analyzer references.