Intel® Quartus® Prime Standard Edition User Guide: Getting Started

ID 683475
Date 12/16/2019
Public
Document Table of Contents

5.4.8. Confine SystemVerilog Features to SystemVerilog Files

Intel® Quartus® Prime Pro Edition synthesis does not allow SystemVerilog features in Verilog HDL files. Other Quartus software products allow use of a subset of SystemVerilog (.sv) features in Verilog HDL (.v) design files. To avoid syntax errors in Intel® Quartus® Prime Pro Edition, allow only SystemVerilog features in Verilog HDL files.
To use SystemVerilog features in your existing Verilog HDL files, rename your Verilog HDL (.v) files as SystemVerilog (.sv) files. Alternatively, you can set the file type in the .qsf, as shown in the following example:
set_global_assignment -name SYSTEMVERILOG_FILE <file>.v
Table 23.  SystemVerilog Feature Differences
Other Quartus Software Products Intel® Quartus® Prime Pro Edition
From the Example RTL, synthesis interprets $clog2 in a .v file, even though the Verilog LRM does not define the $clog2 feature. Other Quartus software products allow other SystemVerilog features in .v files. From the Example RTL, synthesis generates a syntax error for detection of any non-Verilog HDL construct in .v files. Intel® Quartus® Prime Pro Edition synthesis honors SystemVerilog features only in .sv files.

Example RTL:

localparam num_mem_locations = 1050;
wire mem_addr [$clog2(num_mem_locations)-1 : 0];

Did you find the information on this page useful?

Characters remaining:

Feedback Message