1. Introduction to Intel® Quartus® Prime Standard Edition 2. Managing Intel® Quartus® Prime Projects 3. Design Planning 4. Introduction to Intel® FPGA IP Cores 5. Migrating to Intel® Quartus® Prime Pro Edition A. Intel® Quartus® Prime Pro Edition User Guide: Getting Started Documentation Archive B. Intel® Quartus® Prime Standard Edition User Guides
2.1. Viewing Basic Project Information 2.2. Intel® Quartus® Prime Project Contents 2.3. Managing Project Settings 2.4. Managing Logic Design Files 2.5. Managing Timing Constraints 2.6. Integrating Other EDA Tools 2.7. Exporting Compilation Results 2.8. Migrating Projects Across Operating Systems 2.9. Archiving Projects 2.10. Command-Line Interface 2.11. Managing Projects Revision History
3.1. Design Planning 3.2. Create a Design Specification and Test Plan 3.3. Plan for the Target Device 3.4. Plan for Intellectual Property Cores 3.5. Plan for Standard Interfaces 3.6. Plan for Device Programming 3.7. Plan for Device Power Consumption 3.8. Plan for Interface I/O Pins 3.9. Plan for other EDA Tools 3.10. Plan for On-Chip Debugging Tools 3.11. Plan HDL Coding Styles 3.12. Plan for Hierarchical and Team-Based Designs 3.13. Design Planning Revision History
4.1. IP Catalog and Parameter Editor 4.2. Installing and Licensing Intel® FPGA IP Cores 4.3. IP General Settings 4.4. Adding Your Own IP to IP Catalog 4.5. Best Practices for Intel® FPGA IP 4.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 4.7. Modifying an IP Variation 4.8. Upgrading IP Cores 4.9. Simulating Intel® FPGA IP Cores 4.10. Synthesizing IP Cores in Other EDA Tools 4.11. Instantiating IP Cores in HDL 4.12. Introduction to Intel FPGA IP Cores Revision History
5.2.1. Modify Entity Name Assignments 5.2.2. Resolve Timing Constraint Entity Names 5.2.3. Verify Generated Node Name Assignments 5.2.4. Replace Logic Lock (Standard) Regions 5.2.5. Modify Signal Tap Logic Analyzer Files 5.2.6. Remove References to .qip Files 5.2.7. Remove Unsupported Feature Assignments
5.4.1. Verify Verilog Compilation Unit 5.4.2. Update Entity Auto-Discovery 5.4.3. Ensure Distinct VHDL Namespace for Each Library 5.4.4. Remove Unsupported Parameter Passing 5.4.5. Remove Unsized Constant from WYSIWYG Instantiation 5.4.6. Remove Non-Standard Pragmas 5.4.7. Declare Objects Before Initial Values 5.4.8. Confine SystemVerilog Features to SystemVerilog Files 5.4.9. Avoid Assignment Mixing in Always Blocks 5.4.10. Avoid Unconnected, Non-Existent Ports 5.4.11. Avoid Illegal Parameter Ranges 5.4.12. Update Verilog HDL and VHDL Type Mapping
3.10. Plan for On-Chip Debugging Tools
Consider whether to include on-chip debugging tools early in the design process. Adding the debugging tools late in the design process can be more time consuming and error prone.
The Intel® Quartus® Prime in-system debugging tools offer different advantages and trade-offs, depending on the characteristics of your design. Consider the following debugging requirements when planning your design to support debugging tools:
- JTAG connections—required to perform in-system debugging with JTAG tools. Plan your system and board with JTAG ports that are available for debugging.
- Additional logic resources (ALR)—required to implement JTAG hub logic. If you set up the appropriate tool early in your design cycle, you can include these device resources in your early resource estimations to ensure that you do not overload the device with logic.
- Reserve device memory—required if your tool uses device memory to capture data during system operation. To ensure that you have enough memory resources to take advantage of this debugging technique, consider reserving device memory to use during debugging.
- Reserve I/O pins—required if you use the Logic Analyzer Interface (LAI) or Signal Probe tools, which require I/O pins for debugging. If you reserve I/O pins for debugging, you do not have to later change your design or board. The LAI can multiplex signals with design I/O pins if required. Ensure that your board supports a debugging mode, in which debugging signals do not affect system operation.
- Instantiate an IP core in your HDL code—required if your debugging tool uses an Intel FPGA IP core.
- Instantiate the Signal Tap Logic Analyzer IP core—required if you want to manually connect the Signal Tap Logic Analyzer to nodes in your design and ensure that the tapped node names do not change during synthesis.
Note: You can add the Signal Tap Logic Analyzer as a separate design partition for incremental compilation to minimize recompilation times.
Table 7. Factors to Consider When Using Debugging Tools During Design Planning Stages Design Planning Factor Signal Tap
System Console In-System Memory
Logic Analyzer Interface (LAI) Signal Probe In-System Sources
Virtual JTAG IP Core JTAG connections Yes Yes Yes Yes — Yes Yes Additional logic resources — Yes — — — — Yes Reserve device memory Yes Yes — — — — — Reserve I/O pins — — — Yes Yes — — Instantiate IP core in your HDL code — — — — — Yes Yes
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