Intel® Quartus® Prime Standard Edition User Guide: Getting Started

ID 683475
Date 12/16/2019
Document Table of Contents Generating IP Functional Simulation Models ( Intel® Quartus® Prime Standard Edition)

Intel provides IP functional simulation models for some Intel® FPGA IP supporting 40nm FPGA devices.
To generate IP functional simulation models:
  1. Turn on the Generate Simulation Model option when parameterizing the IP core.
  2. When you simulate your design, compile only the .vo or .vho for these IP cores in your simulator. Do not compile the corresponding HDL file. The encrypted HDL file supports synthesis by only the Intel® Quartus® Prime software.
    • Intel® FPGA IP cores that do not require IP functional simulation models for simulation, do not provide the Generate Simulation Model option in the IP core parameter editor.
    • Many recently released Intel® FPGA IP cores support RTL simulation using IEEE Verilog HDL encryption. IEEE encrypted models are significantly faster than IP functional simulation models. Simulate the models in both Verilog HDL and VHDL designs.