AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

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ID 683343
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY x
Features Requirements Design Example Walkthrough Components Parameters Design Example Testbench Clocking Scheme Reset Scheme Interface Signals Register Map Document Revision History for Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Design Example Walkthrough x
Setting Up the Design Examples Changing Number of Channels Configuring PHY Speed IP Regeneration
Configuring PHY Speed x
Changing Speed between 10G and 1G in 1000BaseX mode Changing Speed between 1G, 100M, and 10M SGMII
Design Example Testbench x
Testbench Components Testbench Files Simulating Testbench Test Case
Simulating Testbench x
Using ModelSim Simulator Using VCS Simulator
Test Case x
Test Scenario for Design Example without IEEE 1588v2 Test Scenario for Design Example with IEEE 1588v2
Clocking Scheme x
Clocking Diagram Sync-E Support
Sync-E Support x
Enable Ref Clock Sharing Disable Ref Clock Sharing
Reset Scheme x
Design Example without IEEE 1588v2 Design Example with IEEE 1588v2
Design Example without IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Design Example with IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals MDIO Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals ToD Interface Signals
Register Map x
Master TOD 1G TOD 10G TOD PHY 1G/10G MAC
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

Testbench Files

The following table lists the location of the testbench files.

Testbench files location
Design Examples Location
Design example without IEEE 1588v2 <project directory> /LL_Ethernet_10G_A10_phy_lineside/testbench/<Modelsim or VCS>/testcase<n>
Design example with IEEE 1588v2 <project directory> /LL_Ethernet_10G_A10_phy_lineside_1588/testbench/<Modelsim or VCS>/testcase<n>

The following table describes the files that implement the design example testbench.

Testbench Files
File Name Description
all_modes.mif Memory initialization file (MIF) used for reconfiguration to change speed.
avalon_bfm_wrapper.sv A wrapper for the Avalon BFMs that the avalon_driver.sv file uses.
avalon_driver.sv A SystemVerilog HDL driver that uses the BFMs to form the transmit and receive path, and access the Avalon-MM interface.
avalon_if_params_pkg.sv A SystemVerilog HDL testbench that contains parameters to configure the BFMs. Because the configuration is specific to the DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv A SystemVerilog HDL testbench that monitors the Avalon-ST transmit and receive interfaces.
default_test_params_pkg.sv A SystemVerilog HDL package that contains the default parameter settings of the testbench.
eth_mac_frame.sv A SystemVerilog HDL class that defines the Ethernet frames. The avalon_driver.sv file uses this class.
eth_register_map_params_pkg.sv A SystemVerilog HDL package that maps addresses to the Avalon-MM control registers.
ptp_timestamp.sv A SystemVerilog HDL class that defines the timestamp in the testbench.
tb_run.tcl A Tcl script that starts a simulation session in the ModelSim simulation software.
tb_testcase.sv A SystemVerilog HDL testbench file that controls the flow of the testbench.
tb_top_n.sv The top-level testbench file. This file includes the customized 1G/10GbE MAC, which consists of the device under test (DUT), a client packet generator, and a client packet monitor along with other logic blocks.
wave.do A signal tracing macro script that the ModelSim simulation software uses to display testbench signals.
Level Two Title