AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Document Table of Contents

Enable Ref Clock Sharing

When user set the parameter SHARED_REFCLK_EN to 1, this will enable the ref clock sharing and only 1 set of pll_ref_clk_10g, pll_ref_clk_1g, cdr_ref_clk_10g and cdr_ref_clk_1g is needed. These ref clock signals will be used across all channels. There will be N number of rx_recovered_clk regardless of ref clock sharing setting, where N=number of channels.